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bjorn-helgaasbjorn-helgaas
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Merge branch 'remotes/lorenzo/pci/risc-v'
- sifive: Add pcie_aux clock to prci driver (Greentime Hu) - sifive: Use reset-simple in prci driver for PCIe (Greentime Hu) - Add SiFive FU740 PCIe host controller driver and DT binding (Paul Walmsley, Greentime Hu) * remotes/lorenzo/pci/risc-v: riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC PCI: fu740: Add SiFive FU740 PCIe host controller driver dt-bindings: PCI: Add SiFive FU740 PCIe host controller MAINTAINERS: Add maintainers for SiFive FU740 PCIe driver clk: sifive: Use reset-simple in prci driver for PCIe driver clk: sifive: Add pcie_aux clock in prci driver for PCIe driver
2 parents 180594f + ae80d51 commit 98d771e

13 files changed

Lines changed: 556 additions & 1 deletion

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‎Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml‎

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@@ -0,0 +1,113 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/sifive,fu740-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SiFive FU740 PCIe host controller
8+
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description: |+
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SiFive FU740 PCIe host controller is based on the Synopsys DesignWare
11+
PCI core. It shares common features with the PCIe DesignWare core and
12+
inherits common properties defined in
13+
Documentation/devicetree/bindings/pci/designware-pcie.txt.
14+
15+
maintainers:
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- Paul Walmsley <paul.walmsley@sifive.com>
17+
- Greentime Hu <greentime.hu@sifive.com>
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allOf:
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- $ref: /schemas/pci/pci-bus.yaml#
21+
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properties:
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compatible:
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const: sifive,fu740-pcie
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reg:
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maxItems: 3
28+
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reg-names:
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items:
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- const: dbi
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- const: config
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- const: mgmt
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num-lanes:
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const: 8
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msi-parent: true
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interrupt-names:
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items:
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- const: msi
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- const: inta
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- const: intb
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- const: intc
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- const: intd
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resets:
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description: A phandle to the PCIe power up reset line.
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maxItems: 1
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pwren-gpios:
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description: Should specify the GPIO for controlling the PCI bus device power on.
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maxItems: 1
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reset-gpios:
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maxItems: 1
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required:
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- dma-coherent
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- num-lanes
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- interrupts
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- interrupt-names
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- interrupt-parent
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- interrupt-map-mask
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- interrupt-map
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- clock-names
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- clocks
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- resets
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- pwren-gpios
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- reset-gpios
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unevaluatedProperties: false
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examples:
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- |
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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#include <dt-bindings/clock/sifive-fu740-prci.h>
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pcie@e00000000 {
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compatible = "sifive,fu740-pcie";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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reg = <0xe 0x00000000 0x0 0x80000000>,
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<0xd 0xf0000000 0x0 0x10000000>,
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<0x0 0x100d0000 0x0 0x1000>;
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reg-names = "dbi", "config", "mgmt";
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device_type = "pci";
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dma-coherent;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */
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<0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */
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<0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000>, /* mem */
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<0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */
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num-lanes = <0x8>;
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interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>;
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interrupt-names = "msi", "inta", "intb", "intc", "intd";
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interrupt-parent = <&plic0>;
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
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<0x0 0x0 0x0 0x2 &plic0 58>,
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<0x0 0x0 0x0 0x3 &plic0 59>,
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<0x0 0x0 0x0 0x4 &plic0 60>;
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clock-names = "pcie_aux";
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clocks = <&prci PRCI_CLK_PCIE_AUX>;
109+
resets = <&prci 4>;
110+
pwren-gpios = <&gpio 5 0>;
111+
reset-gpios = <&gpio 8 0>;
112+
};
113+
};

‎MAINTAINERS‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13692,6 +13692,14 @@ S: Maintained
1369213692
F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
1369313693
F: drivers/pci/controller/dwc/*imx6*
1369413694

13695+
PCI DRIVER FOR FU740
13696+
M: Paul Walmsley <paul.walmsley@sifive.com>
13697+
M: Greentime Hu <greentime.hu@sifive.com>
13698+
L: linux-pci@vger.kernel.org
13699+
S: Maintained
13700+
F: Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml
13701+
F: drivers/pci/controller/dwc/pcie-fu740.c
13702+
1369513703
PCI DRIVER FOR INTEL VOLUME MANAGEMENT DEVICE (VMD)
1369613704
M: Jonathan Derrick <jonathan.derrick@intel.com>
1369713705
L: linux-pci@vger.kernel.org

‎arch/riscv/boot/dts/sifive/fu740-c000.dtsi‎

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Original file line numberDiff line numberDiff line change
@@ -159,6 +159,7 @@
159159
reg = <0x0 0x10000000 0x0 0x1000>;
160160
clocks = <&hfclk>, <&rtcclk>;
161161
#clock-cells = <1>;
162+
#reset-cells = <1>;
162163
};
163164
uart0: serial@10010000 {
164165
compatible = "sifive,fu740-c000-uart", "sifive,uart0";
@@ -289,5 +290,37 @@
289290
clocks = <&prci PRCI_CLK_PCLK>;
290291
status = "disabled";
291292
};
293+
pcie@e00000000 {
294+
compatible = "sifive,fu740-pcie";
295+
#address-cells = <3>;
296+
#size-cells = <2>;
297+
#interrupt-cells = <1>;
298+
reg = <0xe 0x00000000 0x0 0x80000000>,
299+
<0xd 0xf0000000 0x0 0x10000000>,
300+
<0x0 0x100d0000 0x0 0x1000>;
301+
reg-names = "dbi", "config", "mgmt";
302+
device_type = "pci";
303+
dma-coherent;
304+
bus-range = <0x0 0xff>;
305+
ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */
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<0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */
307+
<0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000>, /* mem */
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<0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */
309+
num-lanes = <0x8>;
310+
interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>;
311+
interrupt-names = "msi", "inta", "intb", "intc", "intd";
312+
interrupt-parent = <&plic0>;
313+
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
314+
interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
315+
<0x0 0x0 0x0 0x2 &plic0 58>,
316+
<0x0 0x0 0x0 0x3 &plic0 59>,
317+
<0x0 0x0 0x0 0x4 &plic0 60>;
318+
clock-names = "pcie_aux";
319+
clocks = <&prci PRCI_CLK_PCIE_AUX>;
320+
pwren-gpios = <&gpio 5 0>;
321+
reset-gpios = <&gpio 8 0>;
322+
resets = <&prci 4>;
323+
status = "okay";
324+
};
292325
};
293326
};

‎drivers/clk/sifive/Kconfig‎

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Original file line numberDiff line numberDiff line change
@@ -10,6 +10,8 @@ if CLK_SIFIVE
1010

1111
config CLK_SIFIVE_PRCI
1212
bool "PRCI driver for SiFive SoCs"
13+
select RESET_CONTROLLER
14+
select RESET_SIMPLE
1315
select CLK_ANALOGBITS_WRPLL_CLN28HPC
1416
help
1517
Supports the Power Reset Clock interface (PRCI) IP block found in

‎drivers/clk/sifive/fu740-prci.c‎

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Original file line numberDiff line numberDiff line change
@@ -72,6 +72,12 @@ static const struct clk_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = {
7272
.recalc_rate = sifive_prci_hfpclkplldiv_recalc_rate,
7373
};
7474

75+
static const struct clk_ops sifive_fu740_prci_pcie_aux_clk_ops = {
76+
.enable = sifive_prci_pcie_aux_clock_enable,
77+
.disable = sifive_prci_pcie_aux_clock_disable,
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.is_enabled = sifive_prci_pcie_aux_clock_is_enabled,
79+
};
80+
7581
/* List of clock controls provided by the PRCI */
7682
struct __prci_clock __prci_init_clocks_fu740[] = {
7783
[PRCI_CLK_COREPLL] = {
@@ -120,4 +126,9 @@ struct __prci_clock __prci_init_clocks_fu740[] = {
120126
.parent_name = "hfpclkpll",
121127
.ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops,
122128
},
129+
[PRCI_CLK_PCIE_AUX] = {
130+
.name = "pcie_aux",
131+
.parent_name = "hfclk",
132+
.ops = &sifive_fu740_prci_pcie_aux_clk_ops,
133+
},
123134
};

‎drivers/clk/sifive/fu740-prci.h‎

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@@ -9,7 +9,7 @@
99

1010
#include "sifive-prci.h"
1111

12-
#define NUM_CLOCK_FU740 8
12+
#define NUM_CLOCK_FU740 9
1313

1414
extern struct __prci_clock __prci_init_clocks_fu740[NUM_CLOCK_FU740];
1515

‎drivers/clk/sifive/sifive-prci.c‎

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Original file line numberDiff line numberDiff line change
@@ -453,6 +453,47 @@ void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd)
453453
r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); /* barrier */
454454
}
455455

456+
/* PCIE AUX clock APIs for enable, disable. */
457+
int sifive_prci_pcie_aux_clock_is_enabled(struct clk_hw *hw)
458+
{
459+
struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
460+
struct __prci_data *pd = pc->pd;
461+
u32 r;
462+
463+
r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET);
464+
465+
if (r & PRCI_PCIE_AUX_EN_MASK)
466+
return 1;
467+
else
468+
return 0;
469+
}
470+
471+
int sifive_prci_pcie_aux_clock_enable(struct clk_hw *hw)
472+
{
473+
struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
474+
struct __prci_data *pd = pc->pd;
475+
u32 r __maybe_unused;
476+
477+
if (sifive_prci_pcie_aux_clock_is_enabled(hw))
478+
return 0;
479+
480+
__prci_writel(1, PRCI_PCIE_AUX_OFFSET, pd);
481+
r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET); /* barrier */
482+
483+
return 0;
484+
}
485+
486+
void sifive_prci_pcie_aux_clock_disable(struct clk_hw *hw)
487+
{
488+
struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
489+
struct __prci_data *pd = pc->pd;
490+
u32 r __maybe_unused;
491+
492+
__prci_writel(0, PRCI_PCIE_AUX_OFFSET, pd);
493+
r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET); /* barrier */
494+
495+
}
496+
456497
/**
457498
* __prci_register_clocks() - register clock controls in the PRCI
458499
* @dev: Linux struct device
@@ -547,6 +588,19 @@ static int sifive_prci_probe(struct platform_device *pdev)
547588
if (IS_ERR(pd->va))
548589
return PTR_ERR(pd->va);
549590

591+
pd->reset.rcdev.owner = THIS_MODULE;
592+
pd->reset.rcdev.nr_resets = PRCI_RST_NR;
593+
pd->reset.rcdev.ops = &reset_simple_ops;
594+
pd->reset.rcdev.of_node = pdev->dev.of_node;
595+
pd->reset.active_low = true;
596+
pd->reset.membase = pd->va + PRCI_DEVICESRESETREG_OFFSET;
597+
spin_lock_init(&pd->reset.lock);
598+
599+
r = devm_reset_controller_register(&pdev->dev, &pd->reset.rcdev);
600+
if (r) {
601+
dev_err(dev, "could not register reset controller: %d\n", r);
602+
return r;
603+
}
550604
r = __prci_register_clocks(dev, pd, desc);
551605
if (r) {
552606
dev_err(dev, "could not register clocks: %d\n", r);

‎drivers/clk/sifive/sifive-prci.h‎

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Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@
1111

1212
#include <linux/clk/analogbits-wrpll-cln28hpc.h>
1313
#include <linux/clk-provider.h>
14+
#include <linux/reset/reset-simple.h>
1415
#include <linux/platform_device.h>
1516

1617
/*
@@ -67,6 +68,11 @@
6768
#define PRCI_DDRPLLCFG1_CKE_SHIFT 31
6869
#define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT)
6970

71+
/* PCIEAUX */
72+
#define PRCI_PCIE_AUX_OFFSET 0x14
73+
#define PRCI_PCIE_AUX_EN_SHIFT 0
74+
#define PRCI_PCIE_AUX_EN_MASK (0x1 << PRCI_PCIE_AUX_EN_SHIFT)
75+
7076
/* GEMGXLPLLCFG0 */
7177
#define PRCI_GEMGXLPLLCFG0_OFFSET 0x1c
7278
#define PRCI_GEMGXLPLLCFG0_DIVR_SHIFT 0
@@ -116,6 +122,8 @@
116122
#define PRCI_DEVICESRESETREG_CHIPLINK_RST_N_MASK \
117123
(0x1 << PRCI_DEVICESRESETREG_CHIPLINK_RST_N_SHIFT)
118124

125+
#define PRCI_RST_NR 7
126+
119127
/* CLKMUXSTATUSREG */
120128
#define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c
121129
#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1
@@ -216,6 +224,7 @@
216224
*/
217225
struct __prci_data {
218226
void __iomem *va;
227+
struct reset_simple_data reset;
219228
struct clk_hw_onecell_data hw_clks;
220229
};
221230

@@ -296,4 +305,8 @@ unsigned long sifive_prci_tlclksel_recalc_rate(struct clk_hw *hw,
296305
unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct clk_hw *hw,
297306
unsigned long parent_rate);
298307

308+
int sifive_prci_pcie_aux_clock_is_enabled(struct clk_hw *hw);
309+
int sifive_prci_pcie_aux_clock_enable(struct clk_hw *hw);
310+
void sifive_prci_pcie_aux_clock_disable(struct clk_hw *hw);
311+
299312
#endif /* __SIFIVE_CLK_SIFIVE_PRCI_H */

‎drivers/pci/controller/dwc/Kconfig‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -319,4 +319,13 @@ config PCIE_AL
319319
required only for DT-based platforms. ACPI platforms with the
320320
Annapurna Labs PCIe controller don't need to enable this.
321321

322+
config PCIE_FU740
323+
bool "SiFive FU740 PCIe host controller"
324+
depends on PCI_MSI_IRQ_DOMAIN
325+
depends on SOC_SIFIVE || COMPILE_TEST
326+
select PCIE_DW_HOST
327+
help
328+
Say Y here if you want PCIe controller support for the SiFive
329+
FU740.
330+
322331
endmenu

‎drivers/pci/controller/dwc/Makefile‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@ obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
55
obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
66
obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
77
obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
8+
obj-$(CONFIG_PCIE_FU740) += pcie-fu740.o
89
obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
910
obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
1011
obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o

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