Merge tag 'cpufreq-arm-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm

Pull ARM cpufreq updates for 5.19-rc1 from Viresh Kumar:

 - Tegra234 cpufreq support (Sumit Gupta).

 - Mediatek cleanups and enhancements (Wan Jiabing, Rex-BC Chen, and
   Jia-Wei Chang).

* tag 'cpufreq-arm-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm: (21 commits)
  cpufreq: mediatek: Add support for MT8186
  cpufreq: mediatek: Link CCI device to CPU
  dt-bindings: cpufreq: mediatek: Add MediaTek CCI property
  cpufreq: mediatek: Fix potential deadlock problem in mtk_cpufreq_set_target
  cpufreq: mediatek: Add opp notification support
  cpufreq: mediatek: Refine mtk_cpufreq_voltage_tracking()
  cpufreq: mediatek: Move voltage limits to platform data
  cpufreq: mediatek: Unregister platform device on exit
  cpufreq: mediatek: Fix NULL pointer dereference in mediatek-cpufreq
  cpufreq: mediatek: Make sram regulator optional
  cpufreq: mediatek: Record previous target vproc value
  cpufreq: mediatek: Replace old_* with pre_*
  cpufreq: mediatek: Use device print to show logs
  cpufreq: mediatek: Enable clocks and regulators
  cpufreq: mediatek: Remove unused headers
  cpufreq: mediatek: Cleanup variables and error handling in mtk_cpu_dvfs_info_init()
  cpufreq: mediatek: Use module_init and add module_exit
  arm64: tegra: add node for tegra234 cpufreq
  cpufreq: tegra194: Add support for Tegra234
  cpufreq: tegra194: add soc data to support multiple soc
  ...

Author: rafaeljw

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml

@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra-ccplex-cluster.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: NVIDIA Tegra CPU COMPLEX CLUSTER area device tree bindings
+
+maintainers:
+  - Sumit Gupta <sumitg@nvidia.com>
+  - Mikko Perttunen <mperttunen@nvidia.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+  - Thierry Reding <thierry.reding@gmail.com>
+
+description: |+
+  The Tegra CPU COMPLEX CLUSTER area contains memory-mapped
+  registers that initiate CPU frequency/voltage transitions.
+
+properties:
+  $nodename:
+    pattern: "ccplex@([0-9a-f]+)$"
+
+  compatible:
+    enum:
+      - nvidia,tegra186-ccplex-cluster
+      - nvidia,tegra234-ccplex-cluster
+
+  reg:
+    maxItems: 1
+
+  nvidia,bpmp:
+    $ref: '/schemas/types.yaml#/definitions/phandle'
+    description: |
+      Specifies the BPMP node that needs to be queried to get
+      operating point data for all CPUs.
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - nvidia,bpmp
+  - status
+
+examples:
+  - |
+    ccplex@e000000 {
+      compatible = "nvidia,tegra234-ccplex-cluster";
+      reg = <0x0e000000 0x5ffff>;
+      nvidia,bpmp = <&bpmp>;
+      status = "okay";
+    };

Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt

@@ -20,6 +20,13 @@ Optional properties:
 	       Vsram to fit SoC specific needs. When absent, the voltage scaling
 	       flow is handled by hardware, hence no software "voltage tracking" is
 	       needed.
+- mediatek,cci:
+	Used to confirm the link status between cpufreq and mediatek cci. Because
+	cpufreq and mediatek cci could share the same regulator in some MediaTek SoCs.
+	To prevent the issue of high frequency and low voltage, we need to use this
+	property to make sure mediatek cci is ready.
+	For details of mediatek cci, please refer to
+	Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
 - #cooling-cells:
 	For details, please refer to
 	Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml

arch/arm64/boot/dts/nvidia/tegra234.dtsi

@@ -1258,6 +1258,13 @@
 		};
 	};
 
+	ccplex@e000000 {
+		compatible = "nvidia,tegra234-ccplex-cluster";
+		reg = <0x0 0x0e000000 0x0 0x5ffff>;
+		nvidia,bpmp = <&bpmp>;
+		status = "okay";
+	};
+
 	sram@40000000 {
 		compatible = "nvidia,tegra234-sysram", "mmio-sram";
 		reg = <0x0 0x40000000 0x0 0x80000>;