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Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 updates from Will Deacon: "We've got a little less than normal thanks to the holidays in December, but there's the usual summary below. The highlight is probably the 52-bit physical addressing (LPA2) clean-up from Ard. Confidential Computing: - Register a platform device when running in CCA realm mode to enable automatic loading of dependent modules CPU Features: - Update a bunch of system register definitions to pick up new field encodings from the architectural documentation - Add hwcaps and selftests for the new (2024) dpISA extensions Documentation: - Update EL3 (firmware) requirements for booting Linux on modern arm64 designs - Remove stale information about the kernel virtual memory map Miscellaneous: - Minor cleanups and typo fixes Memory management: - Fix vmemmap_check_pmd() to look at the PMD type bits - LPA2 (52-bit physical addressing) cleanups and minor fixes - Adjust physical address space depending upon whether or not LPA2 is enabled Perf and PMUs: - Add port filtering support for NVIDIA's NVLINK-C2C Coresight PMU - Extend AXI filtering support for the DDR PMU on NXP IMX SoCs - Fix Designware PCIe PMU event numbering - Add generic branch events for the Apple M1 CPU PMU - Add support for Marvell Odyssey DDR and LLC-TAD PMUs - Cleanups to the Hisilicon DDRC and Uncore PMU code - Advertise discard mode for the SPE PMU - Add the perf users mailing list to our MAINTAINERS entry" * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (64 commits) Documentation: arm64: Remove stale and redundant virtual memory diagrams perf docs: arm_spe: Document new discard mode perf: arm_spe: Add format option for discard mode MAINTAINERS: Add perf list for drivers/perf/ arm64: Remove duplicate included header drivers/perf: apple_m1: Map generic branch events arm64: rsi: Add automatic arm-cca-guest module loading kselftest/arm64: Add 2024 dpISA extensions to hwcap test KVM: arm64: Allow control of dpISA extensions in ID_AA64ISAR3_EL1 arm64/hwcap: Describe 2024 dpISA extensions to userspace arm64/sysreg: Update ID_AA64SMFR0_EL1 to DDI0601 2024-12 arm64: Filter out SVE hwcaps when FEAT_SVE isn't implemented drivers/perf: hisi: Set correct IRQ affinity for PMUs with no association arm64/sme: Move storage of reg_smidr to __cpuinfo_store_cpu() arm64: mm: Test for pmd_sect() in vmemmap_check_pmd() arm64/mm: Replace open encodings with PXD_TABLE_BIT arm64/mm: Rename pte_mkpresent() as pte_mkvalid() arm64/sysreg: Update ID_AA64ISAR2_EL1 to DDI0601 2024-09 arm64/sysreg: Update ID_AA64ZFR0_EL1 to DDI0601 2024-09 arm64/sysreg: Update ID_AA64FPFR0_EL1 to DDI0601 2024-09 ...
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‎Documentation/admin-guide/perf/dwc_pcie_pmu.rst‎

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@@ -60,7 +60,7 @@ description of available events and configuration options in sysfs, see
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The "format" directory describes format of the config fields of the
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perf_event_attr structure. The "events" directory provides configuration
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templates for all documented events. For example,
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"Rx_PCIe_TLP_Data_Payload" is an equivalent of "eventid=0x22,type=0x1".
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"rx_pcie_tlp_data_payload" is an equivalent of "eventid=0x21,type=0x0".
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The "perf list" command shall list the available events from sysfs, e.g.::
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@@ -79,8 +79,8 @@ Example usage of counting PCIe RX TLP data payload (Units of bytes)::
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The average RX/TX bandwidth can be calculated using the following formula:
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PCIe RX Bandwidth = Rx_PCIe_TLP_Data_Payload / Measure_Time_Window
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PCIe TX Bandwidth = Tx_PCIe_TLP_Data_Payload / Measure_Time_Window
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PCIe RX Bandwidth = rx_pcie_tlp_data_payload / Measure_Time_Window
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PCIe TX Bandwidth = tx_pcie_tlp_data_payload / Measure_Time_Window
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Lane Event Usage
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-------------------------------

‎Documentation/admin-guide/perf/hisi-pmu.rst‎

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@@ -35,7 +35,10 @@ e.g. hisi_sccl1_hha0/rx_operations is RX_OPERATIONS event of HHA index #0 in
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SCCL ID #1.
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The driver also provides a "cpumask" sysfs attribute, which shows the CPU core
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ID used to count the uncore PMU event.
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ID used to count the uncore PMU event. An "associated_cpus" sysfs attribute is
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also provided to show the CPUs associated with this PMU. The "cpumask" indicates
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the CPUs to open the events, usually as a hint for userspaces tools like perf.
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It only contains one associated CPU from the "associated_cpus".
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Example usage of perf::
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‎Documentation/admin-guide/perf/index.rst‎

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@@ -14,6 +14,8 @@ Performance monitor support
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qcom_l2_pmu
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qcom_l3_pmu
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starfive_starlink_pmu
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mrvl-odyssey-ddr-pmu
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mrvl-odyssey-tad-pmu
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arm-ccn
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arm-cmn
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arm-ni

‎Documentation/admin-guide/perf/mrvl-odyssey-ddr-pmu.rst‎

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===================================================================
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Marvell Odyssey DDR PMU Performance Monitoring Unit (PMU UNCORE)
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===================================================================
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Odyssey DRAM Subsystem supports eight counters for monitoring performance
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and software can program those counters to monitor any of the defined
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performance events. Supported performance events include those counted
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at the interface between the DDR controller and the PHY, interface between
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the DDR Controller and the CHI interconnect, or within the DDR Controller.
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Additionally DSS also supports two fixed performance event counters, one
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for ddr reads and the other for ddr writes.
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The counter will be operating in either manual or auto mode.
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The PMU driver exposes the available events and format options under sysfs::
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/sys/bus/event_source/devices/mrvl_ddr_pmu_<>/events/
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/sys/bus/event_source/devices/mrvl_ddr_pmu_<>/format/
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Examples::
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$ perf list | grep ddr
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mrvl_ddr_pmu_<>/ddr_act_bypass_access/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_bsm_alloc/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_bsm_starvation/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_cam_active_access/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_cam_mwr/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_cam_rd_active_access/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_cam_rd_or_wr_access/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_cam_read/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_cam_wr_access/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_cam_write/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_capar_error/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_crit_ref/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_ddr_reads/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_ddr_writes/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_dfi_cmd_is_retry/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_dfi_cycles/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_dfi_parity_poison/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_dfi_rd_data_access/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_dfi_wr_data_access/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_dqsosc_mpc/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_dqsosc_mrr/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_enter_mpsm/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_enter_powerdown/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_enter_selfref/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_hif_pri_rdaccess/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_hif_rd_access/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_hif_rd_or_wr_access/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_hif_rmw_access/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_hif_wr_access/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_hpri_sched_rd_crit_access/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_load_mode/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_lpri_sched_rd_crit_access/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_precharge/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_precharge_for_other/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_precharge_for_rdwr/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_raw_hazard/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_rd_bypass_access/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_rd_crc_error/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_rd_uc_ecc_error/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_rdwr_transitions/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_refresh/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_retry_fifo_full/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_spec_ref/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_tcr_mrr/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_war_hazard/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_waw_hazard/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_win_limit_reached_rd/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_win_limit_reached_wr/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_wr_crc_error/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_wr_trxn_crit_access/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_write_combine/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_zqcl/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_zqlatch/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_zqstart/ [Kernel PMU event]
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$ perf stat -e ddr_cam_read,ddr_cam_write,ddr_cam_active_access,ddr_cam
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rd_or_wr_access,ddr_cam_rd_active_access,ddr_cam_mwr <workload>

‎Documentation/admin-guide/perf/mrvl-odyssey-tad-pmu.rst‎

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====================================================================
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Marvell Odyssey LLC-TAD Performance Monitoring Unit (PMU UNCORE)
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====================================================================
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Each TAD provides eight 64-bit counters for monitoring
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cache behavior.The driver always configures the same counter for
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all the TADs. The user would end up effectively reserving one of
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eight counters in every TAD to look across all TADs.
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The occurrences of events are aggregated and presented to the user
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at the end of running the workload. The driver does not provide a
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way for the user to partition TADs so that different TADs are used for
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different applications.
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The performance events reflect various internal or interface activities.
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By combining the values from multiple performance counters, cache
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performance can be measured in terms such as: cache miss rate, cache
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allocations, interface retry rate, internal resource occupancy, etc.
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The PMU driver exposes the available events and format options under sysfs::
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/sys/bus/event_source/devices/tad/events/
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/sys/bus/event_source/devices/tad/format/
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Examples::
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$ perf list | grep tad
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tad/tad_alloc_any/ [Kernel PMU event]
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tad/tad_alloc_dtg/ [Kernel PMU event]
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tad/tad_alloc_ltg/ [Kernel PMU event]
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tad/tad_hit_any/ [Kernel PMU event]
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tad/tad_hit_dtg/ [Kernel PMU event]
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tad/tad_hit_ltg/ [Kernel PMU event]
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tad/tad_req_msh_in_exlmn/ [Kernel PMU event]
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tad/tad_tag_rd/ [Kernel PMU event]
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tad/tad_tot_cycle/ [Kernel PMU event]
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$ perf stat -e tad_alloc_dtg,tad_alloc_ltg,tad_alloc_any,tad_hit_dtg,tad_hit_ltg,tad_hit_any,tad_tag_rd <workload>

‎Documentation/admin-guide/perf/nvidia-pmu.rst‎

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traffic coverage.
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The events and configuration options of this PMU device are described in sysfs,
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see /sys/bus/event_sources/devices/nvidia_scf_pmu_<socket-id>.
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see /sys/bus/event_source/devices/nvidia_scf_pmu_<socket-id>.
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Example usage:
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the PMU traffic coverage.
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The events and configuration options of this PMU device are described in sysfs,
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see /sys/bus/event_sources/devices/nvidia_nvlink_c2c0_pmu_<socket-id>.
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see /sys/bus/event_source/devices/nvidia_nvlink_c2c0_pmu_<socket-id>.
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Example usage:
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perf stat -a -e nvidia_nvlink_c2c0_pmu_3/event=0x0/
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The NVLink-C2C has two ports that can be connected to one GPU (occupying both
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ports) or to two GPUs (one GPU per port). The user can use "port" bitmap
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parameter to select the port(s) to monitor. Each bit represents the port number,
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e.g. "port=0x1" corresponds to port 0 and "port=0x3" is for port 0 and 1. The
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PMU will monitor both ports by default if not specified.
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Example for port filtering:
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* Count event id 0x0 from the GPU connected with socket 0 on port 0::
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perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=0x0,port=0x1/
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* Count event id 0x0 from the GPUs connected with socket 0 on port 0 and port 1::
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perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=0x0,port=0x3/
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NVLink-C2C1 PMU
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the PMU traffic coverage.
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The events and configuration options of this PMU device are described in sysfs,
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see /sys/bus/event_sources/devices/nvidia_nvlink_c2c1_pmu_<socket-id>.
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see /sys/bus/event_source/devices/nvidia_nvlink_c2c1_pmu_<socket-id>.
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Example usage:
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perf stat -a -e nvidia_nvlink_c2c1_pmu_3/event=0x0/
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The NVLink-C2C has two ports that can be connected to one GPU (occupying both
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ports) or to two GPUs (one GPU per port). The user can use "port" bitmap
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parameter to select the port(s) to monitor. Each bit represents the port number,
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e.g. "port=0x1" corresponds to port 0 and "port=0x3" is for port 0 and 1. The
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PMU will monitor both ports by default if not specified.
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Example for port filtering:
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* Count event id 0x0 from the GPU connected with socket 0 on port 0::
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perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=0x0,port=0x1/
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* Count event id 0x0 from the GPUs connected with socket 0 on port 0 and port 1::
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perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=0x0,port=0x3/
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CNVLink PMU
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for more info about the PMU traffic coverage.
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The events and configuration options of this PMU device are described in sysfs,
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see /sys/bus/event_sources/devices/nvidia_cnvlink_pmu_<socket-id>.
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see /sys/bus/event_source/devices/nvidia_cnvlink_pmu_<socket-id>.
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Each SoC socket can be connected to one or more sockets via CNVLink. The user can
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use "rem_socket" bitmap parameter to select the remote socket(s) to monitor.
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Each bit represents the socket number, e.g. "rem_socket=0xE" corresponds to
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socket 1 to 3.
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/sys/bus/event_sources/devices/nvidia_cnvlink_pmu_<socket-id>/format/rem_socket
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socket 1 to 3. The PMU will monitor all remote sockets by default if not
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specified.
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/sys/bus/event_source/devices/nvidia_cnvlink_pmu_<socket-id>/format/rem_socket
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shows the valid bits that can be set in the "rem_socket" parameter.
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The PMU can not distinguish the remote traffic initiator, therefore it does not
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see /sys/bus/event_sources/devices/nvidia_pcie_pmu_<socket-id>.
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see /sys/bus/event_source/devices/nvidia_pcie_pmu_<socket-id>.
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Each SoC socket can support multiple root ports. The user can use
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"root_port" bitmap parameter to select the port(s) to monitor, i.e.
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"root_port=0xF" corresponds to root port 0 to 3.
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/sys/bus/event_sources/devices/nvidia_pcie_pmu_<socket-id>/format/root_port
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"root_port=0xF" corresponds to root port 0 to 3. The PMU will monitor all root
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ports by default if not specified.
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/sys/bus/event_source/devices/nvidia_pcie_pmu_<socket-id>/format/root_port
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shows the valid bits that can be set in the "root_port" parameter.
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Example usage:

‎Documentation/arch/arm64/booting.rst‎

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- HFGWTR_EL2.nGCS_EL0 (bit 52) must be initialised to 0b1.
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- For CPUs with debug architecture i.e FEAT_Debugv8pN (all versions):
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- If EL3 is present:
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- MDCR_EL3.TDA (bit 9) must be initialized to 0b0
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- For CPUs with FEAT_PMUv3:
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- If EL3 is present:
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- MDCR_EL3.TPM (bit 6) must be initialized to 0b0
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The requirements described above for CPU mode, caches, MMUs, architected
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timers, coherency and system registers apply to all CPUs. All CPUs must
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enter the kernel in the same exception level. Where the values documented

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