Skip to content

Commit 9b725d5

Browse files
torvaldstorvalds
committed
Merge tag 'phy-for-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
Pull phy updates from Vinod Koul: "Core: - Add suuport for "rx-polarity" and "tx-polarity" device tree properties and phy common properties to manage this New Support: - Qualcomm Glymur PCIe Gen4 2-lanes PCIe phy, DP and edp phy, USB UNI PHY and SMB2370 eUSB2 repeater. SC8280xp QMP UFS PHY, Kaanapali PCIe phy and QMP PHY, QCS615 QMP USB3+DP PHY and driver support for that. - SpacemiT PCIe/combo PHY and K1 USB2 PHY driver. - HDMI 2.1 FRL configuration support and driver enabling for rockchip samsung-hdptx driver - TI TCAN1046 phy - Renesas RZ/V2H(P) and RZ/V2N usb3 - Mediatek MT8188 hdmi-phy - Google Tensor SoC USB PHY driver - Apple Type-C PHY Updates: - Subsystem conversion for clock round_rate() to determine_rate() - TI USB3 DT schema conversion - Samsung ExynosAutov920 usb3, combo hsphy and ssphy support" * tag 'phy-for-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (143 commits) phy: ti: phy-j721e-wiz: convert from divider_round_rate() to divider_determine_rate() dt-bindings: phy: ti,control-phy-otghs: convert to DT schema dt-bindings: phy: ti,phy-usb3: convert to DT schema phy: tegra: xusb: Remove unused powered_on variable phy: renesas: rcar-gen3-usb2: add regulator dependency phy: GOOGLE_USB: add TYPEC dependency phy: enter drivers/phy/Makefile even without CONFIG_GENERIC_PHY phy: renesas: rcar-gen3-usb2: Use mux-state for phyrst management phy: renesas: rcar-gen3-usb2: Add regulator for OTG VBUS control phy: renesas: rcar-gen3-usb2: Use devm_pm_runtime_enable() phy: renesas: rcar-gen3-usb2: Factor out VBUS control logic dt-bindings: phy: renesas,usb2-phy: Document RZ/G3E SoC dt-bindings: phy: renesas,usb2-phy: Document mux-states property dt-bindings: phy: renesas,usb2-phy: Document USB VBUS regulator phy: rockchip: samsung-hdptx: Add HDMI 2.1 FRL support phy: rockchip: samsung-hdptx: Extend rk_hdptx_phy_verify_hdmi_config() helper phy: rockchip: samsung-hdptx: Switch to driver specific HDMI config phy: rockchip: samsung-hdptx: Drop hw_rate driver data phy: rockchip: samsung-hdptx: Compute clk rate from PLL config phy: rockchip: samsung-hdptx: Cleanup *_cmn_init_seq lists ...
2 parents 4e15e81 + dbeea86 commit 9b725d5

93 files changed

Lines changed: 11329 additions & 880 deletions

File tree

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

‎Documentation/devicetree/bindings/phy/apple,atcphy.yaml‎

Lines changed: 222 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,222 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/phy/apple,atcphy.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Apple Type-C PHY (ATCPHY)
8+
9+
maintainers:
10+
- Sven Peter <sven@kernel.org>
11+
12+
description: >
13+
The Apple Type-C PHY (ATCPHY) is a combined PHY for USB 2.0, USB 3.x,
14+
USB4/Thunderbolt, and DisplayPort connectivity via Type-C ports found in
15+
Apple Silicon SoCs.
16+
17+
The PHY handles muxing between these different protocols and also provides the
18+
reset controller for the attached DWC3 USB controller.
19+
20+
It is designed for USB4 operation and does not handle individual differential
21+
pairs as distinct DisplayPort lanes. Any reference to lane in this binding
22+
hence refers to two differential pairs (RX and TX) as used in USB terminology.
23+
24+
In order to correctly setup these lanes for the various modes calibration
25+
values copied from Apple's firmware and converted to the format described
26+
below by our bootloader m1n1 are required. Without these only USB2 operation
27+
is possible.
28+
29+
allOf:
30+
- $ref: /schemas/usb/usb-switch.yaml#
31+
32+
$defs:
33+
apple,tunable:
34+
$ref: /schemas/types.yaml#/definitions/uint32-matrix
35+
items:
36+
items:
37+
- description: Register offset
38+
- description: Mask to be applied to the register value
39+
- description: Bits to be set after applying the mask
40+
description: >
41+
List of (register offset, mask, value) tuples copied from Apple's Device
42+
Tree by our bootloader m1n1 and used to configure the PHY. These values
43+
even vary for a single product/device and likely contain calibration
44+
values determined by Apple at manufacturing time.
45+
Unless otherwise noted these tunables are always applied to the core
46+
register region.
47+
48+
properties:
49+
compatible:
50+
oneOf:
51+
- items:
52+
- enum:
53+
- apple,t6000-atcphy
54+
- apple,t6020-atcphy
55+
- apple,t8112-atcphy
56+
- const: apple,t8103-atcphy
57+
- const: apple,t8103-atcphy
58+
59+
reg:
60+
items:
61+
- description: Common controls for all PHYs (USB2/3/4, DisplayPort, TBT)
62+
- description: DisplayPort Alternate Mode PHY specific controls
63+
- description: Type-C PHY AXI to Apple Fabric interconnect controls
64+
- description: USB2 PHY specific controls
65+
- description: USB3 PIPE interface controls
66+
67+
reg-names:
68+
items:
69+
- const: core
70+
- const: lpdptx
71+
- const: axi2af
72+
- const: usb2phy
73+
- const: pipehandler
74+
75+
"#phy-cells":
76+
const: 1
77+
78+
"#reset-cells":
79+
const: 0
80+
81+
mode-switch: true
82+
orientation-switch: true
83+
84+
power-domains:
85+
maxItems: 1
86+
87+
ports:
88+
$ref: /schemas/graph.yaml#/properties/ports
89+
properties:
90+
port@0:
91+
$ref: /schemas/graph.yaml#/properties/port
92+
description: Outgoing connection to the SS port of the Type-C connector.
93+
94+
port@1:
95+
$ref: /schemas/graph.yaml#/properties/port
96+
description: Incoming endpoint from the USB3 controller.
97+
98+
port@2:
99+
$ref: /schemas/graph.yaml#/properties/port
100+
description: Incoming endpoint from the DisplayPort controller.
101+
102+
port@3:
103+
$ref: /schemas/graph.yaml#/properties/port
104+
description: Incoming endpoint from the USB4/Thunderbolt controller.
105+
106+
apple,tunable-common-a:
107+
$ref: "#/$defs/apple,tunable"
108+
description: >
109+
Common tunables required for all modes, applied before tunable-axi2af.
110+
111+
apple,tunable-axi2af:
112+
$ref: "#/$defs/apple,tunable"
113+
description: >
114+
AXI to Apple Fabric tunables, required for all modes. Unlike all other
115+
tunables these are applied to the axi2af region.
116+
117+
apple,tunable-common-b:
118+
$ref: "#/$defs/apple,tunable"
119+
description: >
120+
Common tunables required for all modes, applied after tunable-axi2af.
121+
122+
apple,tunable-lane0-usb:
123+
$ref: "#/$defs/apple,tunable"
124+
description: USB3 tunables for lane 0.
125+
126+
apple,tunable-lane1-usb:
127+
$ref: "#/$defs/apple,tunable"
128+
description: USB3 tunables for lane 1.
129+
130+
apple,tunable-lane0-cio:
131+
$ref: "#/$defs/apple,tunable"
132+
description: USB4/Thunderbolt ("Converged IO") tunables for lane 0.
133+
134+
apple,tunable-lane1-cio:
135+
$ref: "#/$defs/apple,tunable"
136+
description: USB4/Thunderbolt ("Converged IO") tunables for lane 1.
137+
138+
apple,tunable-lane0-dp:
139+
$ref: "#/$defs/apple,tunable"
140+
description: >
141+
DisplayPort tunables for lane 0.
142+
143+
Note that lane here refers to a USB RX and TX pair re-used for DisplayPort
144+
and not to an individual DisplayPort differential lane.
145+
146+
apple,tunable-lane1-dp:
147+
$ref: "#/$defs/apple,tunable"
148+
description: >
149+
DisplayPort tunables for lane 1.
150+
151+
Note that lane here refers to a USB RX and TX pair re-used for DisplayPort
152+
and not to an individual DisplayPort differential lane.
153+
154+
required:
155+
- compatible
156+
- reg
157+
- reg-names
158+
- "#phy-cells"
159+
- "#reset-cells"
160+
- orientation-switch
161+
- mode-switch
162+
- power-domains
163+
- ports
164+
165+
additionalProperties: false
166+
167+
examples:
168+
- |
169+
phy@83000000 {
170+
compatible = "apple,t8103-atcphy";
171+
reg = <0x83000000 0x4c000>,
172+
<0x83050000 0x8000>,
173+
<0x80000000 0x4000>,
174+
<0x82a90000 0x4000>,
175+
<0x82a84000 0x4000>;
176+
reg-names = "core", "lpdptx", "axi2af", "usb2phy",
177+
"pipehandler";
178+
179+
#phy-cells = <1>;
180+
#reset-cells = <0>;
181+
182+
orientation-switch;
183+
mode-switch;
184+
power-domains = <&ps_atc0_usb>;
185+
186+
ports {
187+
#address-cells = <1>;
188+
#size-cells = <0>;
189+
190+
port@0 {
191+
reg = <0>;
192+
193+
endpoint {
194+
remote-endpoint = <&typec_connector_ss>;
195+
};
196+
};
197+
198+
port@1 {
199+
reg = <1>;
200+
201+
endpoint {
202+
remote-endpoint = <&dwc3_ss_out>;
203+
};
204+
};
205+
206+
port@2 {
207+
reg = <2>;
208+
209+
endpoint {
210+
remote-endpoint = <&dcp_dp_out>;
211+
};
212+
};
213+
214+
port@3 {
215+
reg = <3>;
216+
217+
endpoint {
218+
remote-endpoint = <&acio_tbt_out>;
219+
};
220+
};
221+
};
222+
};

‎Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml‎

Lines changed: 70 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,32 @@ properties:
2020
"#phy-cells":
2121
const: 1
2222

23+
"#address-cells":
24+
const: 1
25+
26+
"#size-cells":
27+
const: 0
28+
29+
patternProperties:
30+
"^phy@[0-7]$":
31+
type: object
32+
description: SerDes lane (single RX/TX differential pair)
33+
34+
properties:
35+
reg:
36+
minimum: 0
37+
maximum: 7
38+
description: Lane index as seen in register map
39+
40+
"#phy-cells":
41+
const: 0
42+
43+
required:
44+
- reg
45+
- "#phy-cells"
46+
47+
additionalProperties: false
48+
2349
required:
2450
- compatible
2551
- reg
@@ -32,9 +58,52 @@ examples:
3258
soc {
3359
#address-cells = <2>;
3460
#size-cells = <2>;
35-
serdes_1: phy@1ea0000 {
61+
62+
serdes@1ea0000 {
3663
compatible = "fsl,lynx-28g";
3764
reg = <0x0 0x1ea0000 0x0 0x1e30>;
65+
#address-cells = <1>;
66+
#size-cells = <0>;
3867
#phy-cells = <1>;
68+
69+
phy@0 {
70+
reg = <0>;
71+
#phy-cells = <0>;
72+
};
73+
74+
phy@1 {
75+
reg = <1>;
76+
#phy-cells = <0>;
77+
};
78+
79+
phy@2 {
80+
reg = <2>;
81+
#phy-cells = <0>;
82+
};
83+
84+
phy@3 {
85+
reg = <3>;
86+
#phy-cells = <0>;
87+
};
88+
89+
phy@4 {
90+
reg = <4>;
91+
#phy-cells = <0>;
92+
};
93+
94+
phy@5 {
95+
reg = <5>;
96+
#phy-cells = <0>;
97+
};
98+
99+
phy@6 {
100+
reg = <6>;
101+
#phy-cells = <0>;
102+
};
103+
104+
phy@7 {
105+
reg = <7>;
106+
#phy-cells = <0>;
107+
};
39108
};
40109
};

0 commit comments

Comments
 (0)