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Kan LiangPeter Zijlstra
Kan Liang
authored and
Peter Zijlstra
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perf/x86/intel/uncore: Add Lunar Lake support
The uncore subsystem for Lunar Lake is similar to the previous Meteor Lake. The uncore PerfMon registers are located at both MSR and MMIO space. The ARB and iMC are kept. There is no difference from the Meteor Lake. Move the global control initialization to the first box of the CBOX. The sNCU is moved to the MMIO space. The HBO is newly added and only be accessed from the MMIO space. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20240731141353.759643-3-kan.liang@linux.intel.com
1 parent efb0c9c commit 9bd7dfe

3 files changed

Lines changed: 141 additions & 0 deletions

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‎arch/x86/events/intel/uncore.c‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1816,6 +1816,11 @@ static const struct intel_uncore_init_fun mtl_uncore_init __initconst = {
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.mmio_init = adl_uncore_mmio_init,
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};
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static const struct intel_uncore_init_fun lnl_uncore_init __initconst = {
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.cpu_init = lnl_uncore_cpu_init,
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.mmio_init = lnl_uncore_mmio_init,
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};
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static const struct intel_uncore_init_fun icx_uncore_init __initconst = {
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.cpu_init = icx_uncore_cpu_init,
18211826
.pci_init = icx_uncore_pci_init,
@@ -1896,6 +1901,7 @@ static const struct x86_cpu_id intel_uncore_match[] __initconst = {
18961901
X86_MATCH_VFM(INTEL_ARROWLAKE, &mtl_uncore_init),
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X86_MATCH_VFM(INTEL_ARROWLAKE_U, &mtl_uncore_init),
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X86_MATCH_VFM(INTEL_ARROWLAKE_H, &mtl_uncore_init),
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X86_MATCH_VFM(INTEL_LUNARLAKE_M, &lnl_uncore_init),
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X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &spr_uncore_init),
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X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &spr_uncore_init),
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X86_MATCH_VFM(INTEL_GRANITERAPIDS_X, &gnr_uncore_init),

‎arch/x86/events/intel/uncore.h‎

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Original file line numberDiff line numberDiff line change
@@ -611,10 +611,12 @@ void skl_uncore_cpu_init(void);
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void icl_uncore_cpu_init(void);
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void tgl_uncore_cpu_init(void);
613613
void adl_uncore_cpu_init(void);
614+
void lnl_uncore_cpu_init(void);
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void mtl_uncore_cpu_init(void);
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void tgl_uncore_mmio_init(void);
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void tgl_l_uncore_mmio_init(void);
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void adl_uncore_mmio_init(void);
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void lnl_uncore_mmio_init(void);
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int snb_pci2phy_map_init(int devid);
619621

620622
/* uncore_snbep.c */

‎arch/x86/events/intel/uncore_snb.c‎

Lines changed: 133 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -252,6 +252,7 @@ DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
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DEFINE_UNCORE_FORMAT_ATTR(cmask5, cmask, "config:24-28");
253253
DEFINE_UNCORE_FORMAT_ATTR(cmask8, cmask, "config:24-31");
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DEFINE_UNCORE_FORMAT_ATTR(threshold, threshold, "config:24-29");
255+
DEFINE_UNCORE_FORMAT_ATTR(threshold2, threshold, "config:24-31");
255256

256257
/* Sandy Bridge uncore support */
257258
static void snb_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
@@ -746,6 +747,34 @@ void mtl_uncore_cpu_init(void)
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uncore_msr_uncores = mtl_msr_uncores;
747748
}
748749

750+
static struct intel_uncore_type *lnl_msr_uncores[] = {
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&mtl_uncore_cbox,
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&mtl_uncore_arb,
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NULL
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};
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#define LNL_UNC_MSR_GLOBAL_CTL 0x240e
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static void lnl_uncore_msr_init_box(struct intel_uncore_box *box)
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{
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if (box->pmu->pmu_idx == 0)
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wrmsrl(LNL_UNC_MSR_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN);
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}
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static struct intel_uncore_ops lnl_uncore_msr_ops = {
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.init_box = lnl_uncore_msr_init_box,
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.disable_event = snb_uncore_msr_disable_event,
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.enable_event = snb_uncore_msr_enable_event,
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.read_counter = uncore_msr_read_counter,
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};
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void lnl_uncore_cpu_init(void)
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{
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mtl_uncore_cbox.num_boxes = 4;
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mtl_uncore_cbox.ops = &lnl_uncore_msr_ops;
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uncore_msr_uncores = lnl_msr_uncores;
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}
777+
749778
enum {
750779
SNB_PCI_UNCORE_IMC,
751780
};
@@ -1716,3 +1745,107 @@ void adl_uncore_mmio_init(void)
17161745
}
17171746

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/* end of Alder Lake MMIO uncore support */
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/* Lunar Lake MMIO uncore support */
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#define LNL_UNCORE_PCI_SAFBAR_OFFSET 0x68
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#define LNL_UNCORE_MAP_SIZE 0x1000
1752+
#define LNL_UNCORE_SNCU_BASE 0xE4B000
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#define LNL_UNCORE_SNCU_CTR 0x390
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#define LNL_UNCORE_SNCU_CTRL 0x398
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#define LNL_UNCORE_SNCU_BOX_CTL 0x380
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#define LNL_UNCORE_GLOBAL_CTL 0x700
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#define LNL_UNCORE_HBO_BASE 0xE54000
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#define LNL_UNCORE_HBO_OFFSET -4096
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#define LNL_UNCORE_HBO_CTR 0x570
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#define LNL_UNCORE_HBO_CTRL 0x550
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#define LNL_UNCORE_HBO_BOX_CTL 0x548
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#define LNL_UNC_CTL_THRESHOLD 0xff000000
1764+
#define LNL_UNC_RAW_EVENT_MASK (SNB_UNC_CTL_EV_SEL_MASK | \
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SNB_UNC_CTL_UMASK_MASK | \
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SNB_UNC_CTL_EDGE_DET | \
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SNB_UNC_CTL_INVERT | \
1768+
LNL_UNC_CTL_THRESHOLD)
1769+
1770+
static struct attribute *lnl_uncore_formats_attr[] = {
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&format_attr_event.attr,
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&format_attr_umask.attr,
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&format_attr_edge.attr,
1774+
&format_attr_inv.attr,
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&format_attr_threshold2.attr,
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NULL
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};
1778+
1779+
static const struct attribute_group lnl_uncore_format_group = {
1780+
.name = "format",
1781+
.attrs = lnl_uncore_formats_attr,
1782+
};
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1784+
static void lnl_uncore_hbo_init_box(struct intel_uncore_box *box)
1785+
{
1786+
uncore_get_box_mmio_addr(box, LNL_UNCORE_HBO_BASE,
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LNL_UNCORE_PCI_SAFBAR_OFFSET,
1788+
LNL_UNCORE_HBO_OFFSET);
1789+
}
1790+
1791+
static struct intel_uncore_ops lnl_uncore_hbo_ops = {
1792+
.init_box = lnl_uncore_hbo_init_box,
1793+
MMIO_UNCORE_COMMON_OPS()
1794+
};
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1796+
static struct intel_uncore_type lnl_uncore_hbo = {
1797+
.name = "hbo",
1798+
.num_counters = 4,
1799+
.num_boxes = 2,
1800+
.perf_ctr_bits = 64,
1801+
.perf_ctr = LNL_UNCORE_HBO_CTR,
1802+
.event_ctl = LNL_UNCORE_HBO_CTRL,
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.event_mask = LNL_UNC_RAW_EVENT_MASK,
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.box_ctl = LNL_UNCORE_HBO_BOX_CTL,
1805+
.mmio_map_size = LNL_UNCORE_MAP_SIZE,
1806+
.ops = &lnl_uncore_hbo_ops,
1807+
.format_group = &lnl_uncore_format_group,
1808+
};
1809+
1810+
static void lnl_uncore_sncu_init_box(struct intel_uncore_box *box)
1811+
{
1812+
uncore_get_box_mmio_addr(box, LNL_UNCORE_SNCU_BASE,
1813+
LNL_UNCORE_PCI_SAFBAR_OFFSET,
1814+
0);
1815+
1816+
if (box->io_addr)
1817+
writel(ADL_UNCORE_IMC_CTL_INT, box->io_addr + LNL_UNCORE_GLOBAL_CTL);
1818+
}
1819+
1820+
static struct intel_uncore_ops lnl_uncore_sncu_ops = {
1821+
.init_box = lnl_uncore_sncu_init_box,
1822+
MMIO_UNCORE_COMMON_OPS()
1823+
};
1824+
1825+
static struct intel_uncore_type lnl_uncore_sncu = {
1826+
.name = "sncu",
1827+
.num_counters = 2,
1828+
.num_boxes = 1,
1829+
.perf_ctr_bits = 64,
1830+
.perf_ctr = LNL_UNCORE_SNCU_CTR,
1831+
.event_ctl = LNL_UNCORE_SNCU_CTRL,
1832+
.event_mask = LNL_UNC_RAW_EVENT_MASK,
1833+
.box_ctl = LNL_UNCORE_SNCU_BOX_CTL,
1834+
.mmio_map_size = LNL_UNCORE_MAP_SIZE,
1835+
.ops = &lnl_uncore_sncu_ops,
1836+
.format_group = &lnl_uncore_format_group,
1837+
};
1838+
1839+
static struct intel_uncore_type *lnl_mmio_uncores[] = {
1840+
&adl_uncore_imc,
1841+
&lnl_uncore_hbo,
1842+
&lnl_uncore_sncu,
1843+
NULL
1844+
};
1845+
1846+
void lnl_uncore_mmio_init(void)
1847+
{
1848+
uncore_mmio_uncores = lnl_mmio_uncores;
1849+
}
1850+
1851+
/* end of Lunar Lake MMIO uncore support */

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