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Jagadeesh Konaandersson
Jagadeesh Kona
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andersson
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dt-bindings: clock: qcom: Add SM8550 camera clock controller
Add device tree bindings for the camera clock controller on Qualcomm SM8550 platform. Co-developed-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230707035744.22245-2-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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‎Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml‎

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Qualcomm camera clock control module provides the clocks, resets and power
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domains on SM8450.
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See also:: include/dt-bindings/clock/qcom,sm8450-camcc.h
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See also::
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include/dt-bindings/clock/qcom,sm8450-camcc.h
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include/dt-bindings/clock/qcom,sm8550-camcc.h
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properties:
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compatible:
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const: qcom,sm8450-camcc
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enum:
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- qcom,sm8450-camcc
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- qcom,sm8550-camcc
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clocks:
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‎include/dt-bindings/clock/qcom,sm8550-camcc.h‎

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8550_H
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#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8550_H
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/* CAM_CC clocks */
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#define CAM_CC_BPS_AHB_CLK 0
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#define CAM_CC_BPS_CLK 1
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#define CAM_CC_BPS_CLK_SRC 2
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#define CAM_CC_BPS_FAST_AHB_CLK 3
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#define CAM_CC_CAMNOC_AXI_CLK 4
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#define CAM_CC_CAMNOC_AXI_CLK_SRC 5
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#define CAM_CC_CAMNOC_DCD_XO_CLK 6
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#define CAM_CC_CAMNOC_XO_CLK 7
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#define CAM_CC_CCI_0_CLK 8
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#define CAM_CC_CCI_0_CLK_SRC 9
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#define CAM_CC_CCI_1_CLK 10
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#define CAM_CC_CCI_1_CLK_SRC 11
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#define CAM_CC_CCI_2_CLK 12
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#define CAM_CC_CCI_2_CLK_SRC 13
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#define CAM_CC_CORE_AHB_CLK 14
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#define CAM_CC_CPAS_AHB_CLK 15
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#define CAM_CC_CPAS_BPS_CLK 16
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#define CAM_CC_CPAS_CRE_CLK 17
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#define CAM_CC_CPAS_FAST_AHB_CLK 18
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#define CAM_CC_CPAS_IFE_0_CLK 19
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#define CAM_CC_CPAS_IFE_1_CLK 20
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#define CAM_CC_CPAS_IFE_2_CLK 21
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#define CAM_CC_CPAS_IFE_LITE_CLK 22
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#define CAM_CC_CPAS_IPE_NPS_CLK 23
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#define CAM_CC_CPAS_SBI_CLK 24
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#define CAM_CC_CPAS_SFE_0_CLK 25
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#define CAM_CC_CPAS_SFE_1_CLK 26
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#define CAM_CC_CPHY_RX_CLK_SRC 27
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#define CAM_CC_CRE_AHB_CLK 28
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#define CAM_CC_CRE_CLK 29
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#define CAM_CC_CRE_CLK_SRC 30
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#define CAM_CC_CSI0PHYTIMER_CLK 31
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#define CAM_CC_CSI0PHYTIMER_CLK_SRC 32
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#define CAM_CC_CSI1PHYTIMER_CLK 33
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#define CAM_CC_CSI1PHYTIMER_CLK_SRC 34
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#define CAM_CC_CSI2PHYTIMER_CLK 35
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#define CAM_CC_CSI2PHYTIMER_CLK_SRC 36
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#define CAM_CC_CSI3PHYTIMER_CLK 37
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#define CAM_CC_CSI3PHYTIMER_CLK_SRC 38
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#define CAM_CC_CSI4PHYTIMER_CLK 39
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#define CAM_CC_CSI4PHYTIMER_CLK_SRC 40
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#define CAM_CC_CSI5PHYTIMER_CLK 41
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#define CAM_CC_CSI5PHYTIMER_CLK_SRC 42
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#define CAM_CC_CSI6PHYTIMER_CLK 43
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#define CAM_CC_CSI6PHYTIMER_CLK_SRC 44
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#define CAM_CC_CSI7PHYTIMER_CLK 45
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#define CAM_CC_CSI7PHYTIMER_CLK_SRC 46
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#define CAM_CC_CSID_CLK 47
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#define CAM_CC_CSID_CLK_SRC 48
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#define CAM_CC_CSID_CSIPHY_RX_CLK 49
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#define CAM_CC_CSIPHY0_CLK 50
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#define CAM_CC_CSIPHY1_CLK 51
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#define CAM_CC_CSIPHY2_CLK 52
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#define CAM_CC_CSIPHY3_CLK 53
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#define CAM_CC_CSIPHY4_CLK 54
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#define CAM_CC_CSIPHY5_CLK 55
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#define CAM_CC_CSIPHY6_CLK 56
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#define CAM_CC_CSIPHY7_CLK 57
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#define CAM_CC_DRV_AHB_CLK 58
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#define CAM_CC_DRV_XO_CLK 59
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#define CAM_CC_FAST_AHB_CLK_SRC 60
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#define CAM_CC_GDSC_CLK 61
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#define CAM_CC_ICP_AHB_CLK 62
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#define CAM_CC_ICP_CLK 63
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#define CAM_CC_ICP_CLK_SRC 64
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#define CAM_CC_IFE_0_CLK 65
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#define CAM_CC_IFE_0_CLK_SRC 66
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#define CAM_CC_IFE_0_DSP_CLK 67
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#define CAM_CC_IFE_0_DSP_CLK_SRC 68
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#define CAM_CC_IFE_0_FAST_AHB_CLK 69
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#define CAM_CC_IFE_1_CLK 70
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#define CAM_CC_IFE_1_CLK_SRC 71
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#define CAM_CC_IFE_1_DSP_CLK 72
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#define CAM_CC_IFE_1_DSP_CLK_SRC 73
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#define CAM_CC_IFE_1_FAST_AHB_CLK 74
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#define CAM_CC_IFE_2_CLK 75
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#define CAM_CC_IFE_2_CLK_SRC 76
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#define CAM_CC_IFE_2_DSP_CLK 77
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#define CAM_CC_IFE_2_DSP_CLK_SRC 78
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#define CAM_CC_IFE_2_FAST_AHB_CLK 79
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#define CAM_CC_IFE_LITE_AHB_CLK 80
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#define CAM_CC_IFE_LITE_CLK 81
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#define CAM_CC_IFE_LITE_CLK_SRC 82
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#define CAM_CC_IFE_LITE_CPHY_RX_CLK 83
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#define CAM_CC_IFE_LITE_CSID_CLK 84
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#define CAM_CC_IFE_LITE_CSID_CLK_SRC 85
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#define CAM_CC_IPE_NPS_AHB_CLK 86
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#define CAM_CC_IPE_NPS_CLK 87
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#define CAM_CC_IPE_NPS_CLK_SRC 88
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#define CAM_CC_IPE_NPS_FAST_AHB_CLK 89
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#define CAM_CC_IPE_PPS_CLK 90
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#define CAM_CC_IPE_PPS_FAST_AHB_CLK 91
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#define CAM_CC_JPEG_1_CLK 92
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#define CAM_CC_JPEG_CLK 93
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#define CAM_CC_JPEG_CLK_SRC 94
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#define CAM_CC_MCLK0_CLK 95
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#define CAM_CC_MCLK0_CLK_SRC 96
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#define CAM_CC_MCLK1_CLK 97
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#define CAM_CC_MCLK1_CLK_SRC 98
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#define CAM_CC_MCLK2_CLK 99
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#define CAM_CC_MCLK2_CLK_SRC 100
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#define CAM_CC_MCLK3_CLK 101
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#define CAM_CC_MCLK3_CLK_SRC 102
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#define CAM_CC_MCLK4_CLK 103
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#define CAM_CC_MCLK4_CLK_SRC 104
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#define CAM_CC_MCLK5_CLK 105
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#define CAM_CC_MCLK5_CLK_SRC 106
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#define CAM_CC_MCLK6_CLK 107
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#define CAM_CC_MCLK6_CLK_SRC 108
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#define CAM_CC_MCLK7_CLK 109
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#define CAM_CC_MCLK7_CLK_SRC 110
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#define CAM_CC_PLL0 111
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#define CAM_CC_PLL0_OUT_EVEN 112
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#define CAM_CC_PLL0_OUT_ODD 113
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#define CAM_CC_PLL1 114
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#define CAM_CC_PLL1_OUT_EVEN 115
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#define CAM_CC_PLL2 116
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#define CAM_CC_PLL3 117
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#define CAM_CC_PLL3_OUT_EVEN 118
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#define CAM_CC_PLL4 119
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#define CAM_CC_PLL4_OUT_EVEN 120
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#define CAM_CC_PLL5 121
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#define CAM_CC_PLL5_OUT_EVEN 122
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#define CAM_CC_PLL6 123
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#define CAM_CC_PLL6_OUT_EVEN 124
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#define CAM_CC_PLL7 125
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#define CAM_CC_PLL7_OUT_EVEN 126
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#define CAM_CC_PLL8 127
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#define CAM_CC_PLL8_OUT_EVEN 128
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#define CAM_CC_PLL9 129
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#define CAM_CC_PLL9_OUT_EVEN 130
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#define CAM_CC_PLL10 131
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#define CAM_CC_PLL10_OUT_EVEN 132
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#define CAM_CC_PLL11 133
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#define CAM_CC_PLL11_OUT_EVEN 134
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#define CAM_CC_PLL12 135
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#define CAM_CC_PLL12_OUT_EVEN 136
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#define CAM_CC_QDSS_DEBUG_CLK 137
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#define CAM_CC_QDSS_DEBUG_CLK_SRC 138
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#define CAM_CC_QDSS_DEBUG_XO_CLK 139
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#define CAM_CC_SBI_CLK 140
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#define CAM_CC_SBI_FAST_AHB_CLK 141
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#define CAM_CC_SFE_0_CLK 142
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#define CAM_CC_SFE_0_CLK_SRC 143
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#define CAM_CC_SFE_0_FAST_AHB_CLK 144
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#define CAM_CC_SFE_1_CLK 145
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#define CAM_CC_SFE_1_CLK_SRC 146
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#define CAM_CC_SFE_1_FAST_AHB_CLK 147
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#define CAM_CC_SLEEP_CLK 148
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#define CAM_CC_SLEEP_CLK_SRC 149
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#define CAM_CC_SLOW_AHB_CLK_SRC 150
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#define CAM_CC_XO_CLK_SRC 151
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/* CAM_CC power domains */
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#define CAM_CC_BPS_GDSC 0
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#define CAM_CC_IFE_0_GDSC 1
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#define CAM_CC_IFE_1_GDSC 2
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#define CAM_CC_IFE_2_GDSC 3
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#define CAM_CC_IPE_0_GDSC 4
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#define CAM_CC_SBI_GDSC 5
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#define CAM_CC_SFE_0_GDSC 6
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#define CAM_CC_SFE_1_GDSC 7
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#define CAM_CC_TITAN_TOP_GDSC 8
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/* CAM_CC resets */
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#define CAM_CC_BPS_BCR 0
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#define CAM_CC_DRV_BCR 1
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#define CAM_CC_ICP_BCR 2
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#define CAM_CC_IFE_0_BCR 3
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#define CAM_CC_IFE_1_BCR 4
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#define CAM_CC_IFE_2_BCR 5
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#define CAM_CC_IPE_0_BCR 6
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#define CAM_CC_QDSS_DEBUG_BCR 7
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#define CAM_CC_SBI_BCR 8
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#define CAM_CC_SFE_0_BCR 9
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#define CAM_CC_SFE_1_BCR 10
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#endif

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