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superna9999
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dt-bindings: clk: gxbb-clkc: expose all clock ids
Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every gxbb-clkc ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/ [2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/ Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-7-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
1 parent 05d3b7c commit 9ce8555

2 files changed

Lines changed: 65 additions & 76 deletions

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‎drivers/clk/meson/gxbb.h‎

Lines changed: 0 additions & 76 deletions
Original file line numberDiff line numberDiff line change
@@ -112,82 +112,6 @@
112112
#define HHI_BT656_CLK_CNTL 0x3D4 /* 0xf5 offset in data sheet */
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#define HHI_SAR_CLK_CNTL 0x3D8 /* 0xf6 offset in data sheet */
114114

115-
/*
116-
* CLKID index values
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*
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* These indices are entirely contrived and do not map onto the hardware.
119-
* It has now been decided to expose everything by default in the DT header:
120-
* include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want
121-
* to expose, such as the internal muxes and dividers of composite clocks,
122-
* will remain defined here.
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*/
124-
/* ID 1 is unused (it was used by the non-existing CLKID_CPUCLK before) */
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#define CLKID_MPEG_SEL 10
126-
#define CLKID_MPEG_DIV 11
127-
#define CLKID_SAR_ADC_DIV 99
128-
#define CLKID_MALI_0_DIV 101
129-
#define CLKID_MALI_1_DIV 104
130-
#define CLKID_CTS_AMCLK_SEL 108
131-
#define CLKID_CTS_AMCLK_DIV 109
132-
#define CLKID_CTS_MCLK_I958_SEL 111
133-
#define CLKID_CTS_MCLK_I958_DIV 112
134-
#define CLKID_32K_CLK_SEL 115
135-
#define CLKID_32K_CLK_DIV 116
136-
#define CLKID_SD_EMMC_A_CLK0_SEL 117
137-
#define CLKID_SD_EMMC_A_CLK0_DIV 118
138-
#define CLKID_SD_EMMC_B_CLK0_SEL 120
139-
#define CLKID_SD_EMMC_B_CLK0_DIV 121
140-
#define CLKID_SD_EMMC_C_CLK0_SEL 123
141-
#define CLKID_SD_EMMC_C_CLK0_DIV 124
142-
#define CLKID_VPU_0_DIV 127
143-
#define CLKID_VPU_1_DIV 130
144-
#define CLKID_VAPB_0_DIV 134
145-
#define CLKID_VAPB_1_DIV 137
146-
#define CLKID_HDMI_PLL_PRE_MULT 141
147-
#define CLKID_MPLL0_DIV 142
148-
#define CLKID_MPLL1_DIV 143
149-
#define CLKID_MPLL2_DIV 144
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#define CLKID_MPLL_PREDIV 145
151-
#define CLKID_FCLK_DIV2_DIV 146
152-
#define CLKID_FCLK_DIV3_DIV 147
153-
#define CLKID_FCLK_DIV4_DIV 148
154-
#define CLKID_FCLK_DIV5_DIV 149
155-
#define CLKID_FCLK_DIV7_DIV 150
156-
#define CLKID_VDEC_1_SEL 151
157-
#define CLKID_VDEC_1_DIV 152
158-
#define CLKID_VDEC_HEVC_SEL 154
159-
#define CLKID_VDEC_HEVC_DIV 155
160-
#define CLKID_GEN_CLK_SEL 157
161-
#define CLKID_GEN_CLK_DIV 158
162-
#define CLKID_FIXED_PLL_DCO 160
163-
#define CLKID_HDMI_PLL_DCO 161
164-
#define CLKID_HDMI_PLL_OD 162
165-
#define CLKID_HDMI_PLL_OD2 163
166-
#define CLKID_SYS_PLL_DCO 164
167-
#define CLKID_GP0_PLL_DCO 165
168-
#define CLKID_VID_PLL_SEL 167
169-
#define CLKID_VID_PLL_DIV 168
170-
#define CLKID_VCLK_SEL 169
171-
#define CLKID_VCLK2_SEL 170
172-
#define CLKID_VCLK_INPUT 171
173-
#define CLKID_VCLK2_INPUT 172
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#define CLKID_VCLK_DIV 173
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#define CLKID_VCLK2_DIV 174
176-
#define CLKID_VCLK_DIV2_EN 177
177-
#define CLKID_VCLK_DIV4_EN 178
178-
#define CLKID_VCLK_DIV6_EN 179
179-
#define CLKID_VCLK_DIV12_EN 180
180-
#define CLKID_VCLK2_DIV2_EN 181
181-
#define CLKID_VCLK2_DIV4_EN 182
182-
#define CLKID_VCLK2_DIV6_EN 183
183-
#define CLKID_VCLK2_DIV12_EN 184
184-
#define CLKID_CTS_ENCI_SEL 195
185-
#define CLKID_CTS_ENCP_SEL 196
186-
#define CLKID_CTS_VDAC_SEL 197
187-
#define CLKID_HDMI_TX_SEL 198
188-
#define CLKID_HDMI_SEL 203
189-
#define CLKID_HDMI_DIV 204
190-
191115
/* include the CLKIDs that have been made part of the DT binding */
192116
#include <dt-bindings/clock/gxbb-clkc.h>
193117

‎include/dt-bindings/clock/gxbb-clkc.h‎

Lines changed: 65 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,8 @@
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#define CLKID_FCLK_DIV5 7
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#define CLKID_FCLK_DIV7 8
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#define CLKID_GP0_PLL 9
18+
#define CLKID_MPEG_SEL 10
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#define CLKID_MPEG_DIV 11
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#define CLKID_CLK81 12
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#define CLKID_MPLL0 13
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#define CLKID_MPLL1 14
@@ -102,35 +104,92 @@
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#define CLKID_SD_EMMC_C 96
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#define CLKID_SAR_ADC_CLK 97
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#define CLKID_SAR_ADC_SEL 98
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#define CLKID_SAR_ADC_DIV 99
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#define CLKID_MALI_0_SEL 100
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#define CLKID_MALI_0_DIV 101
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#define CLKID_MALI_0 102
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#define CLKID_MALI_1_SEL 103
112+
#define CLKID_MALI_1_DIV 104
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#define CLKID_MALI_1 105
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#define CLKID_MALI 106
110115
#define CLKID_CTS_AMCLK 107
116+
#define CLKID_CTS_AMCLK_SEL 108
117+
#define CLKID_CTS_AMCLK_DIV 109
111118
#define CLKID_CTS_MCLK_I958 110
119+
#define CLKID_CTS_MCLK_I958_SEL 111
120+
#define CLKID_CTS_MCLK_I958_DIV 112
112121
#define CLKID_CTS_I958 113
113122
#define CLKID_32K_CLK 114
123+
#define CLKID_32K_CLK_SEL 115
124+
#define CLKID_32K_CLK_DIV 116
125+
#define CLKID_SD_EMMC_A_CLK0_SEL 117
126+
#define CLKID_SD_EMMC_A_CLK0_DIV 118
114127
#define CLKID_SD_EMMC_A_CLK0 119
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#define CLKID_SD_EMMC_B_CLK0_SEL 120
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#define CLKID_SD_EMMC_B_CLK0_DIV 121
115130
#define CLKID_SD_EMMC_B_CLK0 122
131+
#define CLKID_SD_EMMC_C_CLK0_SEL 123
132+
#define CLKID_SD_EMMC_C_CLK0_DIV 124
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#define CLKID_SD_EMMC_C_CLK0 125
117134
#define CLKID_VPU_0_SEL 126
135+
#define CLKID_VPU_0_DIV 127
118136
#define CLKID_VPU_0 128
119137
#define CLKID_VPU_1_SEL 129
138+
#define CLKID_VPU_1_DIV 130
120139
#define CLKID_VPU_1 131
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#define CLKID_VPU 132
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#define CLKID_VAPB_0_SEL 133
142+
#define CLKID_VAPB_0_DIV 134
123143
#define CLKID_VAPB_0 135
124144
#define CLKID_VAPB_1_SEL 136
145+
#define CLKID_VAPB_1_DIV 137
125146
#define CLKID_VAPB_1 138
126147
#define CLKID_VAPB_SEL 139
127148
#define CLKID_VAPB 140
149+
#define CLKID_HDMI_PLL_PRE_MULT 141
150+
#define CLKID_MPLL0_DIV 142
151+
#define CLKID_MPLL1_DIV 143
152+
#define CLKID_MPLL2_DIV 144
153+
#define CLKID_MPLL_PREDIV 145
154+
#define CLKID_FCLK_DIV2_DIV 146
155+
#define CLKID_FCLK_DIV3_DIV 147
156+
#define CLKID_FCLK_DIV4_DIV 148
157+
#define CLKID_FCLK_DIV5_DIV 149
158+
#define CLKID_FCLK_DIV7_DIV 150
159+
#define CLKID_VDEC_1_SEL 151
160+
#define CLKID_VDEC_1_DIV 152
128161
#define CLKID_VDEC_1 153
162+
#define CLKID_VDEC_HEVC_SEL 154
163+
#define CLKID_VDEC_HEVC_DIV 155
129164
#define CLKID_VDEC_HEVC 156
165+
#define CLKID_GEN_CLK_SEL 157
166+
#define CLKID_GEN_CLK_DIV 158
130167
#define CLKID_GEN_CLK 159
168+
#define CLKID_FIXED_PLL_DCO 160
169+
#define CLKID_HDMI_PLL_DCO 161
170+
#define CLKID_HDMI_PLL_OD 162
171+
#define CLKID_HDMI_PLL_OD2 163
172+
#define CLKID_SYS_PLL_DCO 164
173+
#define CLKID_GP0_PLL_DCO 165
131174
#define CLKID_VID_PLL 166
175+
#define CLKID_VID_PLL_SEL 167
176+
#define CLKID_VID_PLL_DIV 168
177+
#define CLKID_VCLK_SEL 169
178+
#define CLKID_VCLK2_SEL 170
179+
#define CLKID_VCLK_INPUT 171
180+
#define CLKID_VCLK2_INPUT 172
181+
#define CLKID_VCLK_DIV 173
182+
#define CLKID_VCLK2_DIV 174
132183
#define CLKID_VCLK 175
133184
#define CLKID_VCLK2 176
185+
#define CLKID_VCLK_DIV2_EN 177
186+
#define CLKID_VCLK_DIV4_EN 178
187+
#define CLKID_VCLK_DIV6_EN 179
188+
#define CLKID_VCLK_DIV12_EN 180
189+
#define CLKID_VCLK2_DIV2_EN 181
190+
#define CLKID_VCLK2_DIV4_EN 182
191+
#define CLKID_VCLK2_DIV6_EN 183
192+
#define CLKID_VCLK2_DIV12_EN 184
134193
#define CLKID_VCLK_DIV1 185
135194
#define CLKID_VCLK_DIV2 186
136195
#define CLKID_VCLK_DIV4 187
@@ -141,10 +200,16 @@
141200
#define CLKID_VCLK2_DIV4 192
142201
#define CLKID_VCLK2_DIV6 193
143202
#define CLKID_VCLK2_DIV12 194
203+
#define CLKID_CTS_ENCI_SEL 195
204+
#define CLKID_CTS_ENCP_SEL 196
205+
#define CLKID_CTS_VDAC_SEL 197
206+
#define CLKID_HDMI_TX_SEL 198
144207
#define CLKID_CTS_ENCI 199
145208
#define CLKID_CTS_ENCP 200
146209
#define CLKID_CTS_VDAC 201
147210
#define CLKID_HDMI_TX 202
211+
#define CLKID_HDMI_SEL 203
212+
#define CLKID_HDMI_DIV 204
148213
#define CLKID_HDMI 205
149214
#define CLKID_ACODEC 206
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