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28 | 28 | #define CNL_H_GPI_IS 0x100 |
29 | 29 | #define CNL_H_GPI_IE 0x120 |
30 | 30 |
|
31 | | -#define CNL_GPP(r, s, e, g) \ |
32 | | - { \ |
33 | | - .reg_num = (r), \ |
34 | | - .base = (s), \ |
35 | | - .size = ((e) - (s) + 1), \ |
36 | | - .gpio_base = (g), \ |
37 | | - } |
38 | | - |
39 | 31 | #define CNL_LP_COMMUNITY(b, s, e, g) \ |
40 | 32 | INTEL_COMMUNITY_GPPS(b, s, e, g, CNL_LP) |
41 | 33 |
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@@ -362,32 +354,32 @@ static const struct pinctrl_pin_desc cnlh_pins[] = { |
362 | 354 | }; |
363 | 355 |
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364 | 356 | static const struct intel_padgroup cnlh_community0_gpps[] = { |
365 | | - CNL_GPP(0, 0, 24, 0), /* GPP_A */ |
366 | | - CNL_GPP(1, 25, 50, 32), /* GPP_B */ |
| 357 | + INTEL_GPP(0, 0, 24, 0), /* GPP_A */ |
| 358 | + INTEL_GPP(1, 25, 50, 32), /* GPP_B */ |
367 | 359 | }; |
368 | 360 |
|
369 | 361 | static const struct intel_padgroup cnlh_community1_gpps[] = { |
370 | | - CNL_GPP(0, 51, 74, 64), /* GPP_C */ |
371 | | - CNL_GPP(1, 75, 98, 96), /* GPP_D */ |
372 | | - CNL_GPP(2, 99, 106, 128), /* GPP_G */ |
373 | | - CNL_GPP(3, 107, 114, INTEL_GPIO_BASE_NOMAP), /* AZA */ |
374 | | - CNL_GPP(4, 115, 146, 160), /* vGPIO_0 */ |
375 | | - CNL_GPP(5, 147, 154, INTEL_GPIO_BASE_NOMAP), /* vGPIO_1 */ |
| 362 | + INTEL_GPP(0, 51, 74, 64), /* GPP_C */ |
| 363 | + INTEL_GPP(1, 75, 98, 96), /* GPP_D */ |
| 364 | + INTEL_GPP(2, 99, 106, 128), /* GPP_G */ |
| 365 | + INTEL_GPP(3, 107, 114, INTEL_GPIO_BASE_NOMAP), /* AZA */ |
| 366 | + INTEL_GPP(4, 115, 146, 160), /* vGPIO_0 */ |
| 367 | + INTEL_GPP(5, 147, 154, INTEL_GPIO_BASE_NOMAP), /* vGPIO_1 */ |
376 | 368 | }; |
377 | 369 |
|
378 | 370 | static const struct intel_padgroup cnlh_community3_gpps[] = { |
379 | | - CNL_GPP(0, 155, 178, 192), /* GPP_K */ |
380 | | - CNL_GPP(1, 179, 202, 224), /* GPP_H */ |
381 | | - CNL_GPP(2, 203, 215, 256), /* GPP_E */ |
382 | | - CNL_GPP(3, 216, 239, 288), /* GPP_F */ |
383 | | - CNL_GPP(4, 240, 248, INTEL_GPIO_BASE_NOMAP), /* SPI */ |
| 371 | + INTEL_GPP(0, 155, 178, 192), /* GPP_K */ |
| 372 | + INTEL_GPP(1, 179, 202, 224), /* GPP_H */ |
| 373 | + INTEL_GPP(2, 203, 215, 256), /* GPP_E */ |
| 374 | + INTEL_GPP(3, 216, 239, 288), /* GPP_F */ |
| 375 | + INTEL_GPP(4, 240, 248, INTEL_GPIO_BASE_NOMAP), /* SPI */ |
384 | 376 | }; |
385 | 377 |
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386 | 378 | static const struct intel_padgroup cnlh_community4_gpps[] = { |
387 | | - CNL_GPP(0, 249, 259, INTEL_GPIO_BASE_NOMAP), /* CPU */ |
388 | | - CNL_GPP(1, 260, 268, INTEL_GPIO_BASE_NOMAP), /* JTAG */ |
389 | | - CNL_GPP(2, 269, 286, 320), /* GPP_I */ |
390 | | - CNL_GPP(3, 287, 298, 352), /* GPP_J */ |
| 379 | + INTEL_GPP(0, 249, 259, INTEL_GPIO_BASE_NOMAP), /* CPU */ |
| 380 | + INTEL_GPP(1, 260, 268, INTEL_GPIO_BASE_NOMAP), /* JTAG */ |
| 381 | + INTEL_GPP(2, 269, 286, 320), /* GPP_I */ |
| 382 | + INTEL_GPP(3, 287, 298, 352), /* GPP_J */ |
391 | 383 | }; |
392 | 384 |
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393 | 385 | static const unsigned int cnlh_spi0_pins[] = { 40, 41, 42, 43 }; |
@@ -780,25 +772,25 @@ static const struct intel_function cnllp_functions[] = { |
780 | 772 | }; |
781 | 773 |
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782 | 774 | static const struct intel_padgroup cnllp_community0_gpps[] = { |
783 | | - CNL_GPP(0, 0, 24, 0), /* GPP_A */ |
784 | | - CNL_GPP(1, 25, 50, 32), /* GPP_B */ |
785 | | - CNL_GPP(2, 51, 58, 64), /* GPP_G */ |
786 | | - CNL_GPP(3, 59, 67, INTEL_GPIO_BASE_NOMAP), /* SPI */ |
| 775 | + INTEL_GPP(0, 0, 24, 0), /* GPP_A */ |
| 776 | + INTEL_GPP(1, 25, 50, 32), /* GPP_B */ |
| 777 | + INTEL_GPP(2, 51, 58, 64), /* GPP_G */ |
| 778 | + INTEL_GPP(3, 59, 67, INTEL_GPIO_BASE_NOMAP), /* SPI */ |
787 | 779 | }; |
788 | 780 |
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789 | 781 | static const struct intel_padgroup cnllp_community1_gpps[] = { |
790 | | - CNL_GPP(0, 68, 92, 96), /* GPP_D */ |
791 | | - CNL_GPP(1, 93, 116, 128), /* GPP_F */ |
792 | | - CNL_GPP(2, 117, 140, 160), /* GPP_H */ |
793 | | - CNL_GPP(3, 141, 172, 192), /* vGPIO */ |
794 | | - CNL_GPP(4, 173, 180, 224), /* vGPIO */ |
| 782 | + INTEL_GPP(0, 68, 92, 96), /* GPP_D */ |
| 783 | + INTEL_GPP(1, 93, 116, 128), /* GPP_F */ |
| 784 | + INTEL_GPP(2, 117, 140, 160), /* GPP_H */ |
| 785 | + INTEL_GPP(3, 141, 172, 192), /* vGPIO */ |
| 786 | + INTEL_GPP(4, 173, 180, 224), /* vGPIO */ |
795 | 787 | }; |
796 | 788 |
|
797 | 789 | static const struct intel_padgroup cnllp_community4_gpps[] = { |
798 | | - CNL_GPP(0, 181, 204, 256), /* GPP_C */ |
799 | | - CNL_GPP(1, 205, 228, 288), /* GPP_E */ |
800 | | - CNL_GPP(2, 229, 237, INTEL_GPIO_BASE_NOMAP), /* JTAG */ |
801 | | - CNL_GPP(3, 238, 243, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ |
| 790 | + INTEL_GPP(0, 181, 204, 256), /* GPP_C */ |
| 791 | + INTEL_GPP(1, 205, 228, 288), /* GPP_E */ |
| 792 | + INTEL_GPP(2, 229, 237, INTEL_GPIO_BASE_NOMAP), /* JTAG */ |
| 793 | + INTEL_GPP(3, 238, 243, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ |
802 | 794 | }; |
803 | 795 |
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804 | 796 | static const struct intel_community cnllp_communities[] = { |
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