@@ -177,6 +177,16 @@ static const struct mtk_iommu_iova_region single_domain[] = {
177177 {.iova_base = 0 , .size = SZ_4G },
178178};
179179
180+ static const struct mtk_iommu_iova_region mt8192_multi_dom [] = {
181+ { .iova_base = 0x0 , .size = SZ_4G }, /* disp: 0 ~ 4G */
182+ #if IS_ENABLED (CONFIG_ARCH_DMA_ADDR_T_64BIT )
183+ { .iova_base = SZ_4G , .size = SZ_4G }, /* vdec: 4G ~ 8G */
184+ { .iova_base = SZ_4G * 2 , .size = SZ_4G }, /* CAM/MDP: 8G ~ 12G */
185+ { .iova_base = 0x240000000ULL , .size = 0x4000000 }, /* CCU0 */
186+ { .iova_base = 0x244000000ULL , .size = 0x4000000 }, /* CCU1 */
187+ #endif
188+ };
189+
180190/*
181191 * There may be 1 or 2 M4U HWs, But we always expect they are in the same domain
182192 * for the performance.
@@ -1038,12 +1048,24 @@ static const struct mtk_iommu_plat_data mt8183_data = {
10381048 .larbid_remap = {{0 }, {4 }, {5 }, {6 }, {7 }, {2 }, {3 }, {1 }},
10391049};
10401050
1051+ static const struct mtk_iommu_plat_data mt8192_data = {
1052+ .m4u_plat = M4U_MT8192 ,
1053+ .flags = HAS_BCLK | HAS_SUB_COMM | OUT_ORDER_WR_EN |
1054+ WR_THROT_EN | IOVA_34_EN ,
1055+ .inv_sel_reg = REG_MMU_INV_SEL_GEN2 ,
1056+ .iova_region = mt8192_multi_dom ,
1057+ .iova_region_nr = ARRAY_SIZE (mt8192_multi_dom ),
1058+ .larbid_remap = {{0 }, {1 }, {4 , 5 }, {7 }, {2 }, {9 , 11 , 19 , 20 },
1059+ {0 , 14 , 16 }, {0 , 13 , 18 , 17 }},
1060+ };
1061+
10411062static const struct of_device_id mtk_iommu_of_ids [] = {
10421063 { .compatible = "mediatek,mt2712-m4u" , .data = & mt2712_data },
10431064 { .compatible = "mediatek,mt6779-m4u" , .data = & mt6779_data },
10441065 { .compatible = "mediatek,mt8167-m4u" , .data = & mt8167_data },
10451066 { .compatible = "mediatek,mt8173-m4u" , .data = & mt8173_data },
10461067 { .compatible = "mediatek,mt8183-m4u" , .data = & mt8183_data },
1068+ { .compatible = "mediatek,mt8192-m4u" , .data = & mt8192_data },
10471069 {}
10481070};
10491071
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