@@ -249,6 +249,7 @@ static int i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
249249 struct i40e_aqc_get_set_rss_lut * cmd_resp =
250250 (struct i40e_aqc_get_set_rss_lut * )& desc .params .raw ;
251251 int status ;
252+ u16 flags ;
252253
253254 if (set )
254255 i40e_fill_default_direct_cmd_desc (& desc ,
@@ -261,23 +262,18 @@ static int i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
261262 desc .flags |= cpu_to_le16 ((u16 )I40E_AQ_FLAG_BUF );
262263 desc .flags |= cpu_to_le16 ((u16 )I40E_AQ_FLAG_RD );
263264
264- cmd_resp -> vsi_id =
265- cpu_to_le16 ((u16 )((vsi_id <<
266- I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT ) &
267- I40E_AQC_SET_RSS_LUT_VSI_ID_MASK ));
268- cmd_resp -> vsi_id |= cpu_to_le16 ((u16 )I40E_AQC_SET_RSS_LUT_VSI_VALID );
265+ vsi_id = FIELD_PREP (I40E_AQC_SET_RSS_LUT_VSI_ID_MASK , vsi_id ) |
266+ FIELD_PREP (I40E_AQC_SET_RSS_LUT_VSI_VALID , 1 );
267+ cmd_resp -> vsi_id = cpu_to_le16 (vsi_id );
269268
270269 if (pf_lut )
271- cmd_resp -> flags |= cpu_to_le16 ((u16 )
272- ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
273- I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT ) &
274- I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK ));
270+ flags = FIELD_PREP (I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK ,
271+ I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF );
275272 else
276- cmd_resp -> flags |= cpu_to_le16 ((u16 )
277- ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
278- I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT ) &
279- I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK ));
273+ flags = FIELD_PREP (I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK ,
274+ I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI );
280275
276+ cmd_resp -> flags = cpu_to_le16 (flags );
281277 status = i40e_asq_send_command (hw , & desc , lut , lut_size , NULL );
282278
283279 return status ;
@@ -347,11 +343,9 @@ static int i40e_aq_get_set_rss_key(struct i40e_hw *hw,
347343 desc .flags |= cpu_to_le16 ((u16 )I40E_AQ_FLAG_BUF );
348344 desc .flags |= cpu_to_le16 ((u16 )I40E_AQ_FLAG_RD );
349345
350- cmd_resp -> vsi_id =
351- cpu_to_le16 ((u16 )((vsi_id <<
352- I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT ) &
353- I40E_AQC_SET_RSS_KEY_VSI_ID_MASK ));
354- cmd_resp -> vsi_id |= cpu_to_le16 ((u16 )I40E_AQC_SET_RSS_KEY_VSI_VALID );
346+ vsi_id = FIELD_PREP (I40E_AQC_SET_RSS_KEY_VSI_ID_MASK , vsi_id ) |
347+ FIELD_PREP (I40E_AQC_SET_RSS_KEY_VSI_VALID , 1 );
348+ cmd_resp -> vsi_id = cpu_to_le16 (vsi_id );
355349
356350 status = i40e_asq_send_command (hw , & desc , key , key_size , NULL );
357351
@@ -1289,14 +1283,14 @@ void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
12891283 pin_func = I40E_PIN_FUNC_LED ;
12901284
12911285 gpio_val &= ~I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK ;
1292- gpio_val |= (( pin_func <<
1293- I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT ) &
1294- I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK );
1286+ gpio_val |=
1287+ FIELD_PREP ( I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK ,
1288+ pin_func );
12951289 }
12961290 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK ;
12971291 /* this & is a bit of paranoia, but serves as a range check */
1298- gpio_val |= (( mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT ) &
1299- I40E_GLGEN_GPIO_CTL_LED_MODE_MASK );
1292+ gpio_val |= FIELD_PREP ( I40E_GLGEN_GPIO_CTL_LED_MODE_MASK ,
1293+ mode );
13001294
13011295 if (blink )
13021296 gpio_val |= BIT (I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT );
@@ -3515,8 +3509,7 @@ int i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
35153509 desc .flags |= cpu_to_le16 ((u16 )I40E_AQ_FLAG_BUF );
35163510
35173511 cmd -> type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK ;
3518- cmd -> type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT ) &
3519- I40E_AQ_LLDP_BRIDGE_TYPE_MASK );
3512+ cmd -> type |= FIELD_PREP (I40E_AQ_LLDP_BRIDGE_TYPE_MASK , bridge_type );
35203513
35213514 desc .datalen = cpu_to_le16 (buff_size );
35223515
@@ -4234,30 +4227,25 @@ int i40e_set_filter_control(struct i40e_hw *hw,
42344227
42354228 /* Program required PE hash buckets for the PF */
42364229 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK ;
4237- val |= ((u32 )settings -> pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT ) &
4238- I40E_PFQF_CTL_0_PEHSIZE_MASK ;
4230+ val |= FIELD_PREP (I40E_PFQF_CTL_0_PEHSIZE_MASK , settings -> pe_filt_num );
42394231 /* Program required PE contexts for the PF */
42404232 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK ;
4241- val |= ((u32 )settings -> pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT ) &
4242- I40E_PFQF_CTL_0_PEDSIZE_MASK ;
4233+ val |= FIELD_PREP (I40E_PFQF_CTL_0_PEDSIZE_MASK , settings -> pe_cntx_num );
42434234
42444235 /* Program required FCoE hash buckets for the PF */
42454236 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK ;
4246- val |= ((u32 )settings -> fcoe_filt_num <<
4247- I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT ) &
4248- I40E_PFQF_CTL_0_PFFCHSIZE_MASK ;
4237+ val |= FIELD_PREP (I40E_PFQF_CTL_0_PFFCHSIZE_MASK ,
4238+ settings -> fcoe_filt_num );
42494239 /* Program required FCoE DDP contexts for the PF */
42504240 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK ;
4251- val |= ((u32 )settings -> fcoe_cntx_num <<
4252- I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT ) &
4253- I40E_PFQF_CTL_0_PFFCDSIZE_MASK ;
4241+ val |= FIELD_PREP (I40E_PFQF_CTL_0_PFFCDSIZE_MASK ,
4242+ settings -> fcoe_cntx_num );
42544243
42554244 /* Program Hash LUT size for the PF */
42564245 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK ;
42574246 if (settings -> hash_lut_size == I40E_HASH_LUT_SIZE_512 )
42584247 hash_lut_size = 1 ;
4259- val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT ) &
4260- I40E_PFQF_CTL_0_HASHLUTSIZE_MASK ;
4248+ val |= FIELD_PREP (I40E_PFQF_CTL_0_HASHLUTSIZE_MASK , hash_lut_size );
42614249
42624250 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
42634251 if (settings -> enable_fdir )
@@ -5319,16 +5307,17 @@ static void i40e_mdio_if_number_selection(struct i40e_hw *hw, bool set_mdio,
53195307 u8 mdio_num ,
53205308 struct i40e_aqc_phy_register_access * cmd )
53215309{
5322- if (set_mdio && cmd -> phy_interface == I40E_AQ_PHY_REG_ACCESS_EXTERNAL ) {
5323- if (test_bit (I40E_HW_CAP_AQ_PHY_ACCESS_EXTENDED , hw -> caps ))
5324- cmd -> cmd_flags |=
5325- I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER |
5326- ((mdio_num <<
5327- I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT ) &
5328- I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK );
5329- else
5330- i40e_debug (hw , I40E_DEBUG_PHY ,
5331- "MDIO I/F number selection not supported by current FW version.\n" );
5310+ if (!set_mdio ||
5311+ cmd -> phy_interface != I40E_AQ_PHY_REG_ACCESS_EXTERNAL )
5312+ return ;
5313+
5314+ if (test_bit (I40E_HW_CAP_AQ_PHY_ACCESS_EXTENDED , hw -> caps )) {
5315+ cmd -> cmd_flags |=
5316+ I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER |
5317+ FIELD_PREP (I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK ,
5318+ mdio_num );
5319+ } else {
5320+ i40e_debug (hw , I40E_DEBUG_PHY , "MDIO I/F number selection not supported by current FW version.\n" );
53325321 }
53335322}
53345323
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