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airliedairlied
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Merge tag 'amd-drm-fixes-6.7-2023-12-06' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes
amd-drm-fixes-6.7-2023-12-06: amdgpu: - Disable MCBP on gfx9 - DC vbios fix - eDP fix - dml2 UBSAN fix - SMU 14 fix - RAS fixes - dml KASAN/KCSAN fix - PSP 13 fix - Clockgating fixes - Suspend fix Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231206221102.4995-1-alexander.deucher@amd.com
2 parents 9ac4883 + dab96d8 commit 9f3e1c5

15 files changed

Lines changed: 187 additions & 53 deletions

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‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3791,10 +3791,6 @@ static void amdgpu_device_set_mcbp(struct amdgpu_device *adev)
37913791
adev->gfx.mcbp = true;
37923792
else if (amdgpu_mcbp == 0)
37933793
adev->gfx.mcbp = false;
3794-
else if ((amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 0, 0)) &&
3795-
(amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 0, 0)) &&
3796-
adev->gfx.num_gfx_rings)
3797-
adev->gfx.mcbp = true;
37983794

37993795
if (amdgpu_sriov_vf(adev))
38003796
adev->gfx.mcbp = true;
@@ -4531,6 +4527,8 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
45314527
if (r)
45324528
return r;
45334529

4530+
amdgpu_ttm_set_buffer_funcs_status(adev, false);
4531+
45344532
amdgpu_fence_driver_hw_fini(adev);
45354533

45364534
amdgpu_device_ip_suspend_phase2(adev);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,8 @@
4646
#define MCA_REG__STATUS__ERRORCODEEXT(x) MCA_REG_FIELD(x, 21, 16)
4747
#define MCA_REG__STATUS__ERRORCODE(x) MCA_REG_FIELD(x, 15, 0)
4848

49+
#define MCA_REG__SYND__ERRORINFORMATION(x) MCA_REG_FIELD(x, 17, 0)
50+
4951
enum amdgpu_mca_ip {
5052
AMDGPU_MCA_IP_UNKNOW = -1,
5153
AMDGPU_MCA_IP_PSP = 0,

‎drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,7 @@
2828
#include <linux/reboot.h>
2929
#include <linux/syscalls.h>
3030
#include <linux/pm_runtime.h>
31+
#include <linux/list_sort.h>
3132

3233
#include "amdgpu.h"
3334
#include "amdgpu_ras.h"
@@ -3665,6 +3666,21 @@ static struct ras_err_node *amdgpu_ras_error_node_new(void)
36653666
return err_node;
36663667
}
36673668

3669+
static int ras_err_info_cmp(void *priv, const struct list_head *a, const struct list_head *b)
3670+
{
3671+
struct ras_err_node *nodea = container_of(a, struct ras_err_node, node);
3672+
struct ras_err_node *nodeb = container_of(b, struct ras_err_node, node);
3673+
struct amdgpu_smuio_mcm_config_info *infoa = &nodea->err_info.mcm_info;
3674+
struct amdgpu_smuio_mcm_config_info *infob = &nodeb->err_info.mcm_info;
3675+
3676+
if (unlikely(infoa->socket_id != infob->socket_id))
3677+
return infoa->socket_id - infob->socket_id;
3678+
else
3679+
return infoa->die_id - infob->die_id;
3680+
3681+
return 0;
3682+
}
3683+
36683684
static struct ras_err_info *amdgpu_ras_error_get_info(struct ras_err_data *err_data,
36693685
struct amdgpu_smuio_mcm_config_info *mcm_info)
36703686
{
@@ -3682,6 +3698,7 @@ static struct ras_err_info *amdgpu_ras_error_get_info(struct ras_err_data *err_d
36823698

36833699
err_data->err_list_count++;
36843700
list_add_tail(&err_node->node, &err_data->err_node_list);
3701+
list_sort(NULL, &err_data->err_node_list, ras_err_info_cmp);
36853702

36863703
return &err_node->err_info;
36873704
}

‎drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -129,6 +129,11 @@ static void hdp_v4_0_get_clockgating_state(struct amdgpu_device *adev,
129129
{
130130
int data;
131131

132+
if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 2)) {
133+
/* Default enabled */
134+
*flags |= AMD_CG_SUPPORT_HDP_MGCG;
135+
return;
136+
}
132137
/* AMD_CG_SUPPORT_HDP_LS */
133138
data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
134139
if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)

‎drivers/gpu/drm/amd/amdgpu/psp_v13_0.c‎

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -60,7 +60,7 @@ MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin");
6060
#define GFX_CMD_USB_PD_USE_LFB 0x480
6161

6262
/* Retry times for vmbx ready wait */
63-
#define PSP_VMBX_POLLING_LIMIT 20000
63+
#define PSP_VMBX_POLLING_LIMIT 3000
6464

6565
/* VBIOS gfl defines */
6666
#define MBOX_READY_MASK 0x80000000
@@ -161,14 +161,18 @@ static int psp_v13_0_wait_for_vmbx_ready(struct psp_context *psp)
161161
static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)
162162
{
163163
struct amdgpu_device *adev = psp->adev;
164-
int retry_loop, ret;
164+
int retry_loop, retry_cnt, ret;
165165

166+
retry_cnt =
167+
(amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6)) ?
168+
PSP_VMBX_POLLING_LIMIT :
169+
10;
166170
/* Wait for bootloader to signify that it is ready having bit 31 of
167171
* C2PMSG_35 set to 1. All other bits are expected to be cleared.
168172
* If there is an error in processing command, bits[7:0] will be set.
169173
* This is applicable for PSP v13.0.6 and newer.
170174
*/
171-
for (retry_loop = 0; retry_loop < PSP_VMBX_POLLING_LIMIT; retry_loop++) {
175+
for (retry_loop = 0; retry_loop < retry_cnt; retry_loop++) {
172176
ret = psp_wait_for(
173177
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
174178
0x80000000, 0xffffffff, false);
@@ -821,7 +825,7 @@ static int psp_v13_0_query_boot_status(struct psp_context *psp)
821825
if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6))
822826
return 0;
823827

824-
if (RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_59) < 0x00a10007)
828+
if (RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_59) < 0x00a10109)
825829
return 0;
826830

827831
for_each_inst(i, inst_mask) {

‎drivers/gpu/drm/amd/amdgpu/soc15.c‎

Lines changed: 10 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1423,11 +1423,14 @@ static void soc15_common_get_clockgating_state(void *handle, u64 *flags)
14231423
if (amdgpu_sriov_vf(adev))
14241424
*flags = 0;
14251425

1426-
adev->nbio.funcs->get_clockgating_state(adev, flags);
1426+
if (adev->nbio.funcs && adev->nbio.funcs->get_clockgating_state)
1427+
adev->nbio.funcs->get_clockgating_state(adev, flags);
14271428

1428-
adev->hdp.funcs->get_clock_gating_state(adev, flags);
1429+
if (adev->hdp.funcs && adev->hdp.funcs->get_clock_gating_state)
1430+
adev->hdp.funcs->get_clock_gating_state(adev, flags);
14291431

1430-
if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2)) {
1432+
if ((amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2)) &&
1433+
(amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6))) {
14311434
/* AMD_CG_SUPPORT_DRM_MGCG */
14321435
data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
14331436
if (!(data & 0x01000000))
@@ -1440,9 +1443,11 @@ static void soc15_common_get_clockgating_state(void *handle, u64 *flags)
14401443
}
14411444

14421445
/* AMD_CG_SUPPORT_ROM_MGCG */
1443-
adev->smuio.funcs->get_clock_gating_state(adev, flags);
1446+
if (adev->smuio.funcs && adev->smuio.funcs->get_clock_gating_state)
1447+
adev->smuio.funcs->get_clock_gating_state(adev, flags);
14441448

1445-
adev->df.funcs->get_clockgating_state(adev, flags);
1449+
if (adev->df.funcs && adev->df.funcs->get_clockgating_state)
1450+
adev->df.funcs->get_clockgating_state(adev, flags);
14461451
}
14471452

14481453
static int soc15_common_set_powergating_state(void *handle,

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -63,6 +63,12 @@ static void apply_edid_quirks(struct edid *edid, struct dc_edid_caps *edid_caps)
6363
DRM_DEBUG_DRIVER("Disabling FAMS on monitor with panel id %X\n", panel_id);
6464
edid_caps->panel_patch.disable_fams = true;
6565
break;
66+
/* Workaround for some monitors that do not clear DPCD 0x317 if FreeSync is unsupported */
67+
case drm_edid_encode_panel_id('A', 'U', 'O', 0xA7AB):
68+
case drm_edid_encode_panel_id('A', 'U', 'O', 0xE69B):
69+
DRM_DEBUG_DRIVER("Clearing DPCD 0x317 on monitor with panel id %X\n", panel_id);
70+
edid_caps->panel_patch.remove_sink_ext_caps = true;
71+
break;
6672
default:
6773
return;
6874
}

‎drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c‎

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2386,7 +2386,13 @@ static enum bp_result get_vram_info_v30(
23862386
return BP_RESULT_BADBIOSTABLE;
23872387

23882388
info->num_chans = info_v30->channel_num;
2389-
info->dram_channel_width_bytes = (1 << info_v30->channel_width) / 8;
2389+
/* As suggested by VBIOS we should always use
2390+
* dram_channel_width_bytes = 2 when using VRAM
2391+
* table version 3.0. This is because the channel_width
2392+
* param in the VRAM info table is changed in 7000 series and
2393+
* no longer represents the memory channel width.
2394+
*/
2395+
info->dram_channel_width_bytes = 2;
23902396

23912397
return result;
23922398
}

‎drivers/gpu/drm/amd/display/dc/dml/Makefile‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -61,8 +61,12 @@ endif
6161
endif
6262

6363
ifneq ($(CONFIG_FRAME_WARN),0)
64+
ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y)
65+
frame_warn_flag := -Wframe-larger-than=3072
66+
else
6467
frame_warn_flag := -Wframe-larger-than=2048
6568
endif
69+
endif
6670

6771
CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
6872
CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_ccflags)

‎drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -9447,12 +9447,12 @@ void dml_core_mode_programming(struct display_mode_lib_st *mode_lib, const struc
94479447

94489448
// Output
94499449
CalculateWatermarks_params->Watermark = &s->dummy_watermark; // Watermarks *Watermark
9450-
CalculateWatermarks_params->DRAMClockChangeSupport = &mode_lib->ms.support.DRAMClockChangeSupport[j];
9450+
CalculateWatermarks_params->DRAMClockChangeSupport = &mode_lib->ms.support.DRAMClockChangeSupport[0];
94519451
CalculateWatermarks_params->MaxActiveDRAMClockChangeLatencySupported = &s->dummy_single_array[0][0]; // dml_float_t *MaxActiveDRAMClockChangeLatencySupported[]
94529452
CalculateWatermarks_params->SubViewportLinesNeededInMALL = &mode_lib->ms.SubViewportLinesNeededInMALL[j]; // dml_uint_t SubViewportLinesNeededInMALL[]
9453-
CalculateWatermarks_params->FCLKChangeSupport = &mode_lib->ms.support.FCLKChangeSupport[j];
9453+
CalculateWatermarks_params->FCLKChangeSupport = &mode_lib->ms.support.FCLKChangeSupport[0];
94549454
CalculateWatermarks_params->MaxActiveFCLKChangeLatencySupported = &s->dummy_single[0]; // dml_float_t *MaxActiveFCLKChangeLatencySupported
9455-
CalculateWatermarks_params->USRRetrainingSupport = &mode_lib->ms.support.USRRetrainingSupport[j];
9455+
CalculateWatermarks_params->USRRetrainingSupport = &mode_lib->ms.support.USRRetrainingSupport[0];
94569456

94579457
CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(
94589458
&mode_lib->scratch,

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