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Merge tag 'renesas-clk-for-v5.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven: - Add support for the new RZ/G2UL SoC - Add RPC (QSPI/HyperFlash) clocks on R-Car E3 and D3 - Miscellaneous fixes and improvements * tag 'renesas-clk-for-v5.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r9a07g043: Add SDHI clock and reset entries clk: renesas: r9a07g043: Add GbEthernet clock/reset clk: renesas: r9a07g043: Add ethernet clock sources clk: renesas: r9a07g043: Add GPIO clock and reset entries clk: renesas: Add support for RZ/G2UL SoC clk: renesas: Move RPC core clocks clk: renesas: rzg2l: Simplify multiplication/shift logic dt-bindings: clock: Add R9A07G043 CPG Clock and Reset Definitions clk: renesas: r8a77995: Add RPC clocks clk: renesas: r8a77990: Add RPC clocks dt-bindings: clock: renesas: Document RZ/G2UL SoC clk: renesas: rzg2l: Remove unused notifiers
2 parents 3123109 + 59086e4 commit 9f4f53e

20 files changed

Lines changed: 488 additions & 57 deletions

‎Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ maintainers:
1010
- Geert Uytterhoeven <geert+renesas@glider.be>
1111

1212
description: |
13-
On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module
13+
On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module
1414
Standby Mode share the same register block.
1515
1616
They provide the following functionalities:
@@ -23,8 +23,9 @@ description: |
2323
properties:
2424
compatible:
2525
enum:
26-
- renesas,r9a07g044-cpg # RZ/G2{L,LC}
27-
- renesas,r9a07g054-cpg # RZ/V2L
26+
- renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2}
27+
- renesas,r9a07g044-cpg # RZ/G2{L,LC}
28+
- renesas,r9a07g054-cpg # RZ/V2L
2829

2930
reg:
3031
maxItems: 1

‎drivers/clk/renesas/Kconfig‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,7 @@ config CLK_RENESAS
3333
select CLK_R8A779A0 if ARCH_R8A779A0
3434
select CLK_R8A779F0 if ARCH_R8A779F0
3535
select CLK_R9A06G032 if ARCH_R9A06G032
36+
select CLK_R9A07G043 if ARCH_R9A07G043
3637
select CLK_R9A07G044 if ARCH_R9A07G044
3738
select CLK_R9A07G054 if ARCH_R9A07G054
3839
select CLK_SH73A0 if ARCH_SH73A0
@@ -160,6 +161,10 @@ config CLK_R8A779F0
160161
config CLK_R9A06G032
161162
bool "RZ/N1D clock support" if COMPILE_TEST
162163

164+
config CLK_R9A07G043
165+
bool "RZ/G2UL clock support" if COMPILE_TEST
166+
select CLK_RZG2L
167+
163168
config CLK_R9A07G044
164169
bool "RZ/G2L clock support" if COMPILE_TEST
165170
select CLK_RZG2L
@@ -200,7 +205,7 @@ config CLK_RCAR_USB2_CLOCK_SEL
200205
This is a driver for R-Car USB2 clock selector
201206

202207
config CLK_RZG2L
203-
bool "Renesas RZ/{G2L,V2L} family clock support" if COMPILE_TEST
208+
bool "Renesas RZ/{G2L,G2UL,V2L} family clock support" if COMPILE_TEST
204209
select RESET_CONTROLLER
205210

206211
# Generic

‎drivers/clk/renesas/Makefile‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,7 @@ obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
3030
obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
3131
obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
3232
obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
33+
obj-$(CONFIG_CLK_R9A07G043) += r9a07g043-cpg.o
3334
obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
3435
obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
3536
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o

‎drivers/clk/renesas/r8a774a1-cpg-mssr.c‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -68,12 +68,8 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
6868
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
6969
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
7070
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
71-
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
7271

73-
DEF_BASE("rpc", R8A774A1_CLK_RPC, CLK_TYPE_GEN3_RPC,
74-
CLK_RPCSRC),
75-
DEF_BASE("rpcd2", R8A774A1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
76-
R8A774A1_CLK_RPC),
72+
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
7773

7874
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
7975

@@ -109,6 +105,9 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
109105
DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, R8A774A1_CLK_SD2H, 0x268),
110106
DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, R8A774A1_CLK_SD3H, 0x26c),
111107

108+
DEF_BASE("rpc", R8A774A1_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
109+
DEF_BASE("rpcd2", R8A774A1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774A1_CLK_RPC),
110+
112111
DEF_FIXED("cl", R8A774A1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
113112
DEF_FIXED("cp", R8A774A1_CLK_CP, CLK_EXTAL, 2, 1),
114113
DEF_FIXED("cpex", R8A774A1_CLK_CPEX, CLK_EXTAL, 2, 1),

‎drivers/clk/renesas/r8a774b1-cpg-mssr.c‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -66,12 +66,8 @@ static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = {
6666
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
6767
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
6868
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
69-
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
7069

71-
DEF_BASE("rpc", R8A774B1_CLK_RPC, CLK_TYPE_GEN3_RPC,
72-
CLK_RPCSRC),
73-
DEF_BASE("rpcd2", R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
74-
R8A774B1_CLK_RPC),
70+
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
7571

7672
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
7773

@@ -106,6 +102,9 @@ static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = {
106102
DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, R8A774B1_CLK_SD2H, 0x268),
107103
DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, R8A774B1_CLK_SD3H, 0x26c),
108104

105+
DEF_BASE("rpc", R8A774B1_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
106+
DEF_BASE("rpcd2", R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774B1_CLK_RPC),
107+
109108
DEF_FIXED("cl", R8A774B1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
110109
DEF_FIXED("cp", R8A774B1_CLK_CP, CLK_EXTAL, 2, 1),
111110
DEF_FIXED("cpex", R8A774B1_CLK_CPEX, CLK_EXTAL, 2, 1),

‎drivers/clk/renesas/r8a774c0-cpg-mssr.c‎

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -77,11 +77,6 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = {
7777

7878
DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
7979

80-
DEF_BASE("rpc", R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC,
81-
CLK_RPCSRC),
82-
DEF_BASE("rpcd2", R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
83-
R8A774C0_CLK_RPC),
84-
8580
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
8681

8782
DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
@@ -108,6 +103,9 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = {
108103
DEF_FIXED("s3d2", R8A774C0_CLK_S3D2, CLK_S3, 2, 1),
109104
DEF_FIXED("s3d4", R8A774C0_CLK_S3D4, CLK_S3, 4, 1),
110105

106+
DEF_BASE("rpc", R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
107+
DEF_BASE("rpcd2", R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774C0_CLK_RPC),
108+
111109
DEF_GEN3_SDH("sd0h", R8A774C0_CLK_SD0H, CLK_SDSRC, 0x0074),
112110
DEF_GEN3_SDH("sd1h", R8A774C0_CLK_SD1H, CLK_SDSRC, 0x0078),
113111
DEF_GEN3_SDH("sd3h", R8A774C0_CLK_SD3H, CLK_SDSRC, 0x026c),

‎drivers/clk/renesas/r8a774e1-cpg-mssr.c‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -68,12 +68,8 @@ static const struct cpg_core_clk r8a774e1_core_clks[] __initconst = {
6868
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
6969
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
7070
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
71-
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
7271

73-
DEF_BASE("rpc", R8A774E1_CLK_RPC, CLK_TYPE_GEN3_RPC,
74-
CLK_RPCSRC),
75-
DEF_BASE("rpcd2", R8A774E1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
76-
R8A774E1_CLK_RPC),
72+
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
7773

7874
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
7975

@@ -109,6 +105,9 @@ static const struct cpg_core_clk r8a774e1_core_clks[] __initconst = {
109105
DEF_GEN3_SD("sd2", R8A774E1_CLK_SD2, R8A774E1_CLK_SD2H, 0x268),
110106
DEF_GEN3_SD("sd3", R8A774E1_CLK_SD3, R8A774E1_CLK_SD3H, 0x26c),
111107

108+
DEF_BASE("rpc", R8A774E1_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
109+
DEF_BASE("rpcd2", R8A774E1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774E1_CLK_RPC),
110+
112111
DEF_FIXED("cl", R8A774E1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
113112
DEF_FIXED("cr", R8A774E1_CLK_CR, CLK_PLL1_DIV4, 2, 1),
114113
DEF_FIXED("cp", R8A774E1_CLK_CP, CLK_EXTAL, 2, 1),

‎drivers/clk/renesas/r8a7795-cpg-mssr.c‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -71,12 +71,8 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
7171
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
7272
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
7373
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
74-
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
7574

76-
DEF_BASE("rpc", R8A7795_CLK_RPC, CLK_TYPE_GEN3_RPC,
77-
CLK_RPCSRC),
78-
DEF_BASE("rpcd2", R8A7795_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
79-
R8A7795_CLK_RPC),
75+
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
8076

8177
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
8278

@@ -113,6 +109,9 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
113109
DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, R8A7795_CLK_SD2H, 0x268),
114110
DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, R8A7795_CLK_SD3H, 0x26c),
115111

112+
DEF_BASE("rpc", R8A7795_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
113+
DEF_BASE("rpcd2", R8A7795_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A7795_CLK_RPC),
114+
116115
DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
117116
DEF_FIXED("cr", R8A7795_CLK_CR, CLK_PLL1_DIV4, 2, 1),
118117
DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),

‎drivers/clk/renesas/r8a7796-cpg-mssr.c‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -73,12 +73,8 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
7373
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
7474
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
7575
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
76-
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
7776

78-
DEF_BASE("rpc", R8A7796_CLK_RPC, CLK_TYPE_GEN3_RPC,
79-
CLK_RPCSRC),
80-
DEF_BASE("rpcd2", R8A7796_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
81-
R8A7796_CLK_RPC),
77+
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
8278

8379
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
8480

@@ -115,6 +111,9 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
115111
DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, R8A7796_CLK_SD2H, 0x268),
116112
DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, R8A7796_CLK_SD3H, 0x26c),
117113

114+
DEF_BASE("rpc", R8A7796_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
115+
DEF_BASE("rpcd2", R8A7796_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A7796_CLK_RPC),
116+
118117
DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
119118
DEF_FIXED("cr", R8A7796_CLK_CR, CLK_PLL1_DIV4, 2, 1),
120119
DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),

‎drivers/clk/renesas/r8a77965-cpg-mssr.c‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -69,12 +69,8 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
6969
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
7070
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
7171
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
72-
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
7372

74-
DEF_BASE("rpc", R8A77965_CLK_RPC, CLK_TYPE_GEN3_RPC,
75-
CLK_RPCSRC),
76-
DEF_BASE("rpcd2", R8A77965_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
77-
R8A77965_CLK_RPC),
73+
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
7874

7975
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
8076

@@ -110,6 +106,9 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
110106
DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, R8A77965_CLK_SD2H, 0x268),
111107
DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, R8A77965_CLK_SD3H, 0x26c),
112108

109+
DEF_BASE("rpc", R8A77965_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
110+
DEF_BASE("rpcd2", R8A77965_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77965_CLK_RPC),
111+
113112
DEF_FIXED("cl", R8A77965_CLK_CL, CLK_PLL1_DIV2, 48, 1),
114113
DEF_FIXED("cr", R8A77965_CLK_CR, CLK_PLL1_DIV4, 2, 1),
115114
DEF_FIXED("cp", R8A77965_CLK_CP, CLK_EXTAL, 2, 1),

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