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jnikulajnikula
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drm/i915/power: convert assert_chv_phy_status() to struct intel_display
struct intel_display will replace struct drm_i915_private as the main device pointer for display code. Switch assert_chv_phy_status() and its callers to it. Main motivation to do just one function is to stop passing i915 to intel_de_wait(), so its generic wrapper can be removed. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/de6b01e1f21934ff520aa3b49ab5f97cbbf028f2.1730146000.git.jani.nikula@intel.com
1 parent 6400c0b commit a00d086

1 file changed

Lines changed: 50 additions & 45 deletions

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‎drivers/gpu/drm/i915/display/intel_display_power_well.c‎

Lines changed: 50 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -1337,13 +1337,14 @@ static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
13371337

13381338
#define BITS_SET(val, bits) (((val) & (bits)) == (bits))
13391339

1340-
static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
1340+
static void assert_chv_phy_status(struct intel_display *display)
13411341
{
1342+
struct drm_i915_private *dev_priv = to_i915(display->drm);
13421343
struct i915_power_well *cmn_bc =
13431344
lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
13441345
struct i915_power_well *cmn_d =
13451346
lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
1346-
u32 phy_control = dev_priv->display.power.chv_phy_control;
1347+
u32 phy_control = display->power.chv_phy_control;
13471348
u32 phy_status = 0;
13481349
u32 phy_status_mask = 0xffffffff;
13491350

@@ -1354,15 +1355,15 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
13541355
* reset (ie. the power well has been disabled at
13551356
* least once).
13561357
*/
1357-
if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY0])
1358+
if (!display->power.chv_phy_assert[DPIO_PHY0])
13581359
phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
13591360
PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
13601361
PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
13611362
PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
13621363
PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
13631364
PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
13641365

1365-
if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY1])
1366+
if (!display->power.chv_phy_assert[DPIO_PHY1])
13661367
phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
13671368
PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
13681369
PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
@@ -1390,7 +1391,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
13901391
*/
13911392
if (BITS_SET(phy_control,
13921393
PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1393-
(intel_de_read(dev_priv, DPLL(dev_priv, PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1394+
(intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VCO_ENABLE) == 0)
13941395
phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
13951396

13961397
if (BITS_SET(phy_control,
@@ -1433,24 +1434,25 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
14331434
* The PHY may be busy with some initial calibration and whatnot,
14341435
* so the power state can take a while to actually change.
14351436
*/
1436-
if (intel_de_wait(dev_priv, DISPLAY_PHY_STATUS,
1437+
if (intel_de_wait(display, DISPLAY_PHY_STATUS,
14371438
phy_status_mask, phy_status, 10))
1438-
drm_err(&dev_priv->drm,
1439+
drm_err(display->drm,
14391440
"Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1440-
intel_de_read(dev_priv, DISPLAY_PHY_STATUS) & phy_status_mask,
1441-
phy_status, dev_priv->display.power.chv_phy_control);
1441+
intel_de_read(display, DISPLAY_PHY_STATUS) & phy_status_mask,
1442+
phy_status, display->power.chv_phy_control);
14421443
}
14431444

14441445
#undef BITS_SET
14451446

14461447
static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
14471448
struct i915_power_well *power_well)
14481449
{
1450+
struct intel_display *display = &dev_priv->display;
14491451
enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
14501452
enum dpio_phy phy;
14511453
u32 tmp;
14521454

1453-
drm_WARN_ON_ONCE(&dev_priv->drm,
1455+
drm_WARN_ON_ONCE(display->drm,
14541456
id != VLV_DISP_PW_DPIO_CMN_BC &&
14551457
id != CHV_DISP_PW_DPIO_CMN_D);
14561458

@@ -1464,9 +1466,9 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
14641466
vlv_set_power_well(dev_priv, power_well, true);
14651467

14661468
/* Poll for phypwrgood signal */
1467-
if (intel_de_wait_for_set(dev_priv, DISPLAY_PHY_STATUS,
1469+
if (intel_de_wait_for_set(display, DISPLAY_PHY_STATUS,
14681470
PHY_POWERGOOD(phy), 1))
1469-
drm_err(&dev_priv->drm, "Display PHY %d is not power up\n",
1471+
drm_err(display->drm, "Display PHY %d is not power up\n",
14701472
phy);
14711473

14721474
vlv_dpio_get(dev_priv);
@@ -1494,24 +1496,25 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
14941496

14951497
vlv_dpio_put(dev_priv);
14961498

1497-
dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1498-
intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
1499-
dev_priv->display.power.chv_phy_control);
1499+
display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1500+
intel_de_write(display, DISPLAY_PHY_CONTROL,
1501+
display->power.chv_phy_control);
15001502

1501-
drm_dbg_kms(&dev_priv->drm,
1503+
drm_dbg_kms(display->drm,
15021504
"Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1503-
phy, dev_priv->display.power.chv_phy_control);
1505+
phy, display->power.chv_phy_control);
15041506

1505-
assert_chv_phy_status(dev_priv);
1507+
assert_chv_phy_status(display);
15061508
}
15071509

15081510
static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
15091511
struct i915_power_well *power_well)
15101512
{
1513+
struct intel_display *display = &dev_priv->display;
15111514
enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
15121515
enum dpio_phy phy;
15131516

1514-
drm_WARN_ON_ONCE(&dev_priv->drm,
1517+
drm_WARN_ON_ONCE(display->drm,
15151518
id != VLV_DISP_PW_DPIO_CMN_BC &&
15161519
id != CHV_DISP_PW_DPIO_CMN_D);
15171520

@@ -1524,20 +1527,20 @@ static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
15241527
assert_pll_disabled(dev_priv, PIPE_C);
15251528
}
15261529

1527-
dev_priv->display.power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1528-
intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
1529-
dev_priv->display.power.chv_phy_control);
1530+
display->power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1531+
intel_de_write(display, DISPLAY_PHY_CONTROL,
1532+
display->power.chv_phy_control);
15301533

15311534
vlv_set_power_well(dev_priv, power_well, false);
15321535

1533-
drm_dbg_kms(&dev_priv->drm,
1536+
drm_dbg_kms(display->drm,
15341537
"Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1535-
phy, dev_priv->display.power.chv_phy_control);
1538+
phy, display->power.chv_phy_control);
15361539

15371540
/* PHY is fully reset now, so we can enable the PHY state asserts */
1538-
dev_priv->display.power.chv_phy_assert[phy] = true;
1541+
display->power.chv_phy_assert[phy] = true;
15391542

1540-
assert_chv_phy_status(dev_priv);
1543+
assert_chv_phy_status(display);
15411544
}
15421545

15431546
static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
@@ -1607,29 +1610,30 @@ static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpi
16071610
bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
16081611
enum dpio_channel ch, bool override)
16091612
{
1610-
struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1613+
struct intel_display *display = &dev_priv->display;
1614+
struct i915_power_domains *power_domains = &display->power.domains;
16111615
bool was_override;
16121616

16131617
mutex_lock(&power_domains->lock);
16141618

1615-
was_override = dev_priv->display.power.chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1619+
was_override = display->power.chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
16161620

16171621
if (override == was_override)
16181622
goto out;
16191623

16201624
if (override)
1621-
dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1625+
display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
16221626
else
1623-
dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1627+
display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
16241628

1625-
intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
1626-
dev_priv->display.power.chv_phy_control);
1629+
intel_de_write(display, DISPLAY_PHY_CONTROL,
1630+
display->power.chv_phy_control);
16271631

1628-
drm_dbg_kms(&dev_priv->drm,
1632+
drm_dbg_kms(display->drm,
16291633
"Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1630-
phy, ch, dev_priv->display.power.chv_phy_control);
1634+
phy, ch, display->power.chv_phy_control);
16311635

1632-
assert_chv_phy_status(dev_priv);
1636+
assert_chv_phy_status(display);
16331637

16341638
out:
16351639
mutex_unlock(&power_domains->lock);
@@ -1640,29 +1644,30 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
16401644
void chv_phy_powergate_lanes(struct intel_encoder *encoder,
16411645
bool override, unsigned int mask)
16421646
{
1647+
struct intel_display *display = to_intel_display(encoder);
16431648
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1644-
struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1649+
struct i915_power_domains *power_domains = &display->power.domains;
16451650
enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder));
16461651
enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder));
16471652

16481653
mutex_lock(&power_domains->lock);
16491654

1650-
dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1651-
dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1655+
display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1656+
display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
16521657

16531658
if (override)
1654-
dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1659+
display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
16551660
else
1656-
dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1661+
display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
16571662

1658-
intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
1659-
dev_priv->display.power.chv_phy_control);
1663+
intel_de_write(display, DISPLAY_PHY_CONTROL,
1664+
display->power.chv_phy_control);
16601665

1661-
drm_dbg_kms(&dev_priv->drm,
1666+
drm_dbg_kms(display->drm,
16621667
"Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1663-
phy, ch, mask, dev_priv->display.power.chv_phy_control);
1668+
phy, ch, mask, display->power.chv_phy_control);
16641669

1665-
assert_chv_phy_status(dev_priv);
1670+
assert_chv_phy_status(display);
16661671

16671672
assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
16681673

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