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cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init()
In preparation for changing how the driver handles 'mem_enable' in the CXL DVSEC control register. Merge the contents of cxl_hdm_decode_init() into cxl_dvsec_ranges() and rename the combined function cxl_hdm_decode_init(). The possible cleanups and fixes that result from this merge are saved for a follow-on change. Reviewed-by: Ira Weiny <ira.weiny@intel.com> Link: https://lore.kernel.org/r/165291690027.1426646.10249756632415633752.stgit@dwillia2-xfh Signed-off-by: Dan Williams <dan.j.williams@intel.com>
1 parent dd2d42a commit a12562b

6 files changed

Lines changed: 83 additions & 104 deletions

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‎drivers/cxl/core/pci.c‎

Lines changed: 75 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -175,13 +175,71 @@ static int wait_for_valid(struct cxl_dev_state *cxlds)
175175
return -ETIMEDOUT;
176176
}
177177

178-
/*
179-
* Return positive number of non-zero ranges on success and a negative
180-
* error code on failure. The cxl_mem driver depends on ranges == 0 to
181-
* init HDM operation.
178+
static bool __cxl_hdm_decode_init(struct cxl_dev_state *cxlds,
179+
struct cxl_endpoint_dvsec_info *info)
180+
{
181+
struct cxl_register_map map;
182+
struct cxl_component_reg_map *cmap = &map.component_map;
183+
bool global_enable, retval = false;
184+
void __iomem *crb;
185+
u32 global_ctrl;
186+
187+
/* map hdm decoder */
188+
crb = ioremap(cxlds->component_reg_phys, CXL_COMPONENT_REG_BLOCK_SIZE);
189+
if (!crb) {
190+
dev_dbg(cxlds->dev, "Failed to map component registers\n");
191+
return false;
192+
}
193+
194+
cxl_probe_component_regs(cxlds->dev, crb, cmap);
195+
if (!cmap->hdm_decoder.valid) {
196+
dev_dbg(cxlds->dev, "Invalid HDM decoder registers\n");
197+
goto out;
198+
}
199+
200+
global_ctrl = readl(crb + cmap->hdm_decoder.offset +
201+
CXL_HDM_DECODER_CTRL_OFFSET);
202+
global_enable = global_ctrl & CXL_HDM_DECODER_ENABLE;
203+
204+
/*
205+
* Per CXL 2.0 Section 8.1.3.8.3 and 8.1.3.8.4 DVSEC CXL Range 1 Base
206+
* [High,Low] when HDM operation is enabled the range register values
207+
* are ignored by the device, but the spec also recommends matching the
208+
* DVSEC Range 1,2 to HDM Decoder Range 0,1. So, non-zero info->ranges
209+
* are expected even though Linux does not require or maintain that
210+
* match.
211+
*/
212+
if (!global_enable && info->mem_enabled && info->ranges)
213+
goto out;
214+
215+
retval = true;
216+
217+
/*
218+
* Permanently (for this boot at least) opt the device into HDM
219+
* operation. Individual HDM decoders still need to be enabled after
220+
* this point.
221+
*/
222+
if (!global_enable) {
223+
dev_dbg(cxlds->dev, "Enabling HDM decode\n");
224+
writel(global_ctrl | CXL_HDM_DECODER_ENABLE,
225+
crb + cmap->hdm_decoder.offset +
226+
CXL_HDM_DECODER_CTRL_OFFSET);
227+
}
228+
229+
out:
230+
iounmap(crb);
231+
return retval;
232+
}
233+
234+
/**
235+
* cxl_hdm_decode_init() - Setup HDM decoding for the endpoint
236+
* @cxlds: Device state
237+
* @info: DVSEC Range cached enumeration
238+
*
239+
* Try to enable the endpoint's HDM Decoder Capability
182240
*/
183-
int cxl_dvsec_ranges(struct cxl_dev_state *cxlds,
184-
struct cxl_endpoint_dvsec_info *info)
241+
int cxl_hdm_decode_init(struct cxl_dev_state *cxlds,
242+
struct cxl_endpoint_dvsec_info *info)
185243
{
186244
struct pci_dev *pdev = to_pci_dev(cxlds->dev);
187245
int hdm_count, rc, i, ranges = 0;
@@ -270,6 +328,16 @@ int cxl_dvsec_ranges(struct cxl_dev_state *cxlds,
270328

271329
info->ranges = ranges;
272330

331+
/*
332+
* If DVSEC ranges are being used instead of HDM decoder registers there
333+
* is no use in trying to manage those.
334+
*/
335+
if (!__cxl_hdm_decode_init(cxlds, info)) {
336+
dev_err(dev,
337+
"Legacy range registers configuration prevents HDM operation.\n");
338+
return -EBUSY;
339+
}
340+
273341
return 0;
274342
}
275-
EXPORT_SYMBOL_NS_GPL(cxl_dvsec_ranges, CXL);
343+
EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, CXL);

‎drivers/cxl/cxlpci.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -74,6 +74,6 @@ static inline resource_size_t cxl_regmap_to_base(struct pci_dev *pdev,
7474
int devm_cxl_port_enumerate_dports(struct cxl_port *port);
7575
struct cxl_dev_state;
7676
struct cxl_endpoint_dvsec_info;
77-
int cxl_dvsec_ranges(struct cxl_dev_state *cxlds,
78-
struct cxl_endpoint_dvsec_info *info);
77+
int cxl_hdm_decode_init(struct cxl_dev_state *cxlds,
78+
struct cxl_endpoint_dvsec_info *info);
7979
#endif /* __CXL_PCI_H__ */

‎drivers/cxl/mem.c‎

Lines changed: 1 addition & 79 deletions
Original file line numberDiff line numberDiff line change
@@ -46,74 +46,6 @@ static int create_endpoint(struct cxl_memdev *cxlmd,
4646
return cxl_endpoint_autoremove(cxlmd, endpoint);
4747
}
4848

49-
/**
50-
* cxl_hdm_decode_init() - Setup HDM decoding for the endpoint
51-
* @cxlds: Device state
52-
*
53-
* Additionally, enables global HDM decoding. Warning: don't call this outside
54-
* of probe. Once probe is complete, the port driver owns all access to the HDM
55-
* decoder registers.
56-
*
57-
* Returns: false if DVSEC Ranges are being used instead of HDM
58-
* decoders, or if it can not be determined if DVSEC Ranges are in use.
59-
* Otherwise, returns true.
60-
*/
61-
__mock bool cxl_hdm_decode_init(struct cxl_dev_state *cxlds,
62-
struct cxl_endpoint_dvsec_info *info)
63-
{
64-
struct cxl_register_map map;
65-
struct cxl_component_reg_map *cmap = &map.component_map;
66-
bool global_enable, retval = false;
67-
void __iomem *crb;
68-
u32 global_ctrl;
69-
70-
/* map hdm decoder */
71-
crb = ioremap(cxlds->component_reg_phys, CXL_COMPONENT_REG_BLOCK_SIZE);
72-
if (!crb) {
73-
dev_dbg(cxlds->dev, "Failed to map component registers\n");
74-
return false;
75-
}
76-
77-
cxl_probe_component_regs(cxlds->dev, crb, cmap);
78-
if (!cmap->hdm_decoder.valid) {
79-
dev_dbg(cxlds->dev, "Invalid HDM decoder registers\n");
80-
goto out;
81-
}
82-
83-
global_ctrl = readl(crb + cmap->hdm_decoder.offset +
84-
CXL_HDM_DECODER_CTRL_OFFSET);
85-
global_enable = global_ctrl & CXL_HDM_DECODER_ENABLE;
86-
87-
/*
88-
* Per CXL 2.0 Section 8.1.3.8.3 and 8.1.3.8.4 DVSEC CXL Range 1 Base
89-
* [High,Low] when HDM operation is enabled the range register values
90-
* are ignored by the device, but the spec also recommends matching the
91-
* DVSEC Range 1,2 to HDM Decoder Range 0,1. So, non-zero info->ranges
92-
* are expected even though Linux does not require or maintain that
93-
* match.
94-
*/
95-
if (!global_enable && info->mem_enabled && info->ranges)
96-
goto out;
97-
98-
retval = true;
99-
100-
/*
101-
* Permanently (for this boot at least) opt the device into HDM
102-
* operation. Individual HDM decoders still need to be enabled after
103-
* this point.
104-
*/
105-
if (!global_enable) {
106-
dev_dbg(cxlds->dev, "Enabling HDM decode\n");
107-
writel(global_ctrl | CXL_HDM_DECODER_ENABLE,
108-
crb + cmap->hdm_decoder.offset +
109-
CXL_HDM_DECODER_CTRL_OFFSET);
110-
}
111-
112-
out:
113-
iounmap(crb);
114-
return retval;
115-
}
116-
11749
static void enable_suspend(void *data)
11850
{
11951
cxl_mem_active_dec();
@@ -163,7 +95,7 @@ static int cxl_mem_probe(struct device *dev)
16395
if (rc)
16496
return rc;
16597

166-
rc = cxl_dvsec_ranges(cxlds, &info);
98+
rc = cxl_hdm_decode_init(cxlds, &info);
16799
if (rc)
168100
return rc;
169101

@@ -173,16 +105,6 @@ static int cxl_mem_probe(struct device *dev)
173105
return rc;
174106
}
175107

176-
/*
177-
* If DVSEC ranges are being used instead of HDM decoder registers there
178-
* is no use in trying to manage those.
179-
*/
180-
if (!cxl_hdm_decode_init(cxlds, &info)) {
181-
dev_err(dev,
182-
"Legacy range registers configuration prevents HDM operation.\n");
183-
return -EBUSY;
184-
}
185-
186108
/*
187109
* The kernel may be operating out of CXL memory on this device,
188110
* there is no spec defined way to determine whether this device

‎tools/testing/cxl/Kbuild‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@ ldflags-y += --wrap=devm_cxl_setup_hdm
99
ldflags-y += --wrap=devm_cxl_add_passthrough_decoder
1010
ldflags-y += --wrap=devm_cxl_enumerate_decoders
1111
ldflags-y += --wrap=cxl_await_media_ready
12-
ldflags-y += --wrap=cxl_dvsec_ranges
12+
ldflags-y += --wrap=cxl_hdm_decode_init
1313

1414
DRIVERS := ../../../drivers
1515
CXL_SRC := $(DRIVERS)/cxl
@@ -36,7 +36,6 @@ cxl_port-y += config_check.o
3636
obj-m += cxl_mem.o
3737

3838
cxl_mem-y := $(CXL_SRC)/mem.o
39-
cxl_mem-y += mock_mem.o
4039
cxl_mem-y += config_check.o
4140

4241
obj-m += cxl_core.o

‎tools/testing/cxl/mock_mem.c‎

Lines changed: 0 additions & 10 deletions
This file was deleted.

‎tools/testing/cxl/test/mock.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -208,21 +208,21 @@ int __wrap_cxl_await_media_ready(struct cxl_dev_state *cxlds)
208208
}
209209
EXPORT_SYMBOL_NS_GPL(__wrap_cxl_await_media_ready, CXL);
210210

211-
int __wrap_cxl_dvsec_ranges(struct cxl_dev_state *cxlds,
212-
struct cxl_endpoint_dvsec_info *info)
211+
int __wrap_cxl_hdm_decode_init(struct cxl_dev_state *cxlds,
212+
struct cxl_endpoint_dvsec_info *info)
213213
{
214214
int rc = 0, index;
215215
struct cxl_mock_ops *ops = get_cxl_mock_ops(&index);
216216

217217
if (ops && ops->is_mock_dev(cxlds->dev))
218218
info->mem_enabled = 1;
219219
else
220-
rc = cxl_dvsec_ranges(cxlds, info);
220+
rc = cxl_hdm_decode_init(cxlds, info);
221221
put_cxl_mock_ops(index);
222222

223223
return rc;
224224
}
225-
EXPORT_SYMBOL_NS_GPL(__wrap_cxl_dvsec_ranges, CXL);
225+
EXPORT_SYMBOL_NS_GPL(__wrap_cxl_hdm_decode_init, CXL);
226226

227227
MODULE_LICENSE("GPL v2");
228228
MODULE_IMPORT_NS(ACPI);

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