Skip to content

Commit a145bbf

Browse files
sureshg20alexdeucher
sureshg20
authored and
alexdeucher
committed
drm/amdgpu/psp: Use Indirect access address for GFX to PSP mailbox
The reason the RAP is not granting access to 0x58200 is that a dedicated RSMU slot would have to be spent for this address range, and MPASP is close to running out of RSMU slots. This will help to fix PSP TOC load failure during secureboot. GFX Driver Need to use indirect access for SMN address regs. Signed-off-by: sguttula <suresh.guttula@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 9b822e2)
1 parent 2c1030f commit a145bbf

2 files changed

Lines changed: 28 additions & 10 deletions

File tree

‎drivers/gpu/drm/amd/amdgpu/psp_v15_0.c‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -69,12 +69,12 @@ static int psp_v15_0_0_ring_stop(struct psp_context *psp,
6969
0x80000000, 0x80000000, false);
7070
} else {
7171
/* Write the ring destroy command*/
72-
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64,
72+
WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64,
7373
GFX_CTRL_CMD_ID_DESTROY_RINGS);
7474
/* there might be handshake issue with hardware which needs delay */
7575
mdelay(20);
7676
/* Wait for response flag (bit 31) */
77-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
77+
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64),
7878
0x80000000, 0x80000000, false);
7979
}
8080

@@ -116,7 +116,7 @@ static int psp_v15_0_0_ring_create(struct psp_context *psp,
116116

117117
} else {
118118
/* Wait for sOS ready for ring creation */
119-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
119+
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64),
120120
0x80000000, 0x80000000, false);
121121
if (ret) {
122122
DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
@@ -125,23 +125,23 @@ static int psp_v15_0_0_ring_create(struct psp_context *psp,
125125

126126
/* Write low address of the ring to C2PMSG_69 */
127127
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
128-
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_69, psp_ring_reg);
128+
WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_69, psp_ring_reg);
129129
/* Write high address of the ring to C2PMSG_70 */
130130
psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
131-
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_70, psp_ring_reg);
131+
WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_70, psp_ring_reg);
132132
/* Write size of ring to C2PMSG_71 */
133133
psp_ring_reg = ring->ring_size;
134-
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_71, psp_ring_reg);
134+
WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_71, psp_ring_reg);
135135
/* Write the ring initialization command to C2PMSG_64 */
136136
psp_ring_reg = ring_type;
137137
psp_ring_reg = psp_ring_reg << 16;
138-
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64, psp_ring_reg);
138+
WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64, psp_ring_reg);
139139

140140
/* there might be handshake issue with hardware which needs delay */
141141
mdelay(20);
142142

143143
/* Wait for response flag (bit 31) in C2PMSG_64 */
144-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
144+
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64),
145145
0x80000000, 0x8000FFFF, false);
146146
}
147147

@@ -174,7 +174,7 @@ static uint32_t psp_v15_0_0_ring_get_wptr(struct psp_context *psp)
174174
if (amdgpu_sriov_vf(adev))
175175
data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102);
176176
else
177-
data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67);
177+
data = RREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_67);
178178

179179
return data;
180180
}
@@ -188,7 +188,7 @@ static void psp_v15_0_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
188188
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101,
189189
GFX_CTRL_CMD_ID_CONSUME_CMD);
190190
} else
191-
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67, value);
191+
WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_67, value);
192192
}
193193

194194
static const struct psp_funcs psp_v15_0_0_funcs = {

‎drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_0_offset.h‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -82,6 +82,24 @@
8282
#define regMPASP_SMN_IH_SW_INT_CTRL 0x0142
8383
#define regMPASP_SMN_IH_SW_INT_CTRL_BASE_IDX 0
8484

85+
// addressBlock: mp_SmuMpASPPub_PcruDec
86+
// base address: 0x3800000
87+
#define regMPASP_PCRU1_MPASP_C2PMSG_64 0x4280
88+
#define regMPASP_PCRU1_MPASP_C2PMSG_64_BASE_IDX 3
89+
#define regMPASP_PCRU1_MPASP_C2PMSG_65 0x4281
90+
#define regMPASP_PCRU1_MPASP_C2PMSG_65_BASE_IDX 3
91+
#define regMPASP_PCRU1_MPASP_C2PMSG_66 0x4282
92+
#define regMPASP_PCRU1_MPASP_C2PMSG_66_BASE_IDX 3
93+
#define regMPASP_PCRU1_MPASP_C2PMSG_67 0x4283
94+
#define regMPASP_PCRU1_MPASP_C2PMSG_67_BASE_IDX 3
95+
#define regMPASP_PCRU1_MPASP_C2PMSG_68 0x4284
96+
#define regMPASP_PCRU1_MPASP_C2PMSG_68_BASE_IDX 3
97+
#define regMPASP_PCRU1_MPASP_C2PMSG_69 0x4285
98+
#define regMPASP_PCRU1_MPASP_C2PMSG_69_BASE_IDX 3
99+
#define regMPASP_PCRU1_MPASP_C2PMSG_70 0x4286
100+
#define regMPASP_PCRU1_MPASP_C2PMSG_70_BASE_IDX 3
101+
#define regMPASP_PCRU1_MPASP_C2PMSG_71 0x4287
102+
#define regMPASP_PCRU1_MPASP_C2PMSG_71_BASE_IDX 3
85103

86104
// addressBlock: mp_SmuMp1_SmnDec
87105
// base address: 0x0

0 commit comments

Comments
 (0)