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clk: renesas: r9a06g032: Improve readability
Several small readability improvements: - Move enum gate_type definition up and add comments to each field. - Use this enum instead of generic uint32_t type in clock desc struct. - Tidy up bitfield syntax and comments in clock desc structure - Reformat macros for building clock desc to have one assignment per line There is no functional change. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230301215520.828455-2-ralph.siemsen@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Lines changed: 80 additions & 41 deletions

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‎drivers/clk/renesas/r9a06g032-clocks.c‎

Lines changed: 80 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -34,64 +34,103 @@ struct r9a06g032_gate {
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scon, mirack, mistat;
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};
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37+
enum gate_type {
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K_GATE = 0, /* gate which enable/disable */
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K_FFC, /* fixed factor clock */
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K_DIV, /* divisor */
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K_BITSEL, /* special for UARTs */
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K_DUALGATE /* special for UARTs */
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};
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/* This is used to describe a clock for instantiation */
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struct r9a06g032_clkdesc {
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const char *name;
40-
uint32_t managed: 1;
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uint32_t type: 3;
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uint32_t index: 8;
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uint32_t source : 8; /* source index + 1 (0 == none) */
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/* these are used to populate the bitsel struct */
48+
uint32_t managed:1;
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enum gate_type type:3;
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uint32_t index:8;
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uint32_t source:8; /* source index + 1 (0 == none) */
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union {
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/* type = K_GATE */
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struct r9a06g032_gate gate;
47-
/* for dividers */
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/* type = K_DIV */
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struct {
49-
unsigned int div_min : 10, div_max : 10, reg: 10;
57+
unsigned int div_min:10, div_max:10, reg:10;
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u16 div_table[4];
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};
52-
/* For fixed-factor ones */
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/* type = K_FFC */
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struct {
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u16 div, mul;
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};
56-
/* for dual gate */
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/* type = K_DUALGATE */
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struct {
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uint16_t group : 1;
66+
uint16_t group:1;
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u16 sel, g1, r1, g2, r2;
6068
} dual;
6169
};
6270
};
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64-
#define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) \
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{ .gate = _clk, .reset = _rst, \
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.ready = _rdy, .midle = _midle, \
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.scon = _scon, .mirack = _mirack, .mistat = _mistat }
68-
#define D_GATE(_idx, _n, _src, ...) \
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{ .type = K_GATE, .index = R9A06G032_##_idx, \
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.source = 1 + R9A06G032_##_src, .name = _n, \
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.gate = I_GATE(__VA_ARGS__) }
72-
#define D_MODULE(_idx, _n, _src, ...) \
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{ .type = K_GATE, .index = R9A06G032_##_idx, \
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.source = 1 + R9A06G032_##_src, .name = _n, \
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.managed = 1, .gate = I_GATE(__VA_ARGS__) }
76-
#define D_ROOT(_idx, _n, _mul, _div) \
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{ .type = K_FFC, .index = R9A06G032_##_idx, .name = _n, \
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.div = _div, .mul = _mul }
79-
#define D_FFC(_idx, _n, _src, _div) \
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{ .type = K_FFC, .index = R9A06G032_##_idx, \
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.source = 1 + R9A06G032_##_src, .name = _n, \
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.div = _div, .mul = 1}
83-
#define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) \
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{ .type = K_DIV, .index = R9A06G032_##_idx, \
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.source = 1 + R9A06G032_##_src, .name = _n, \
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.reg = _reg, .div_min = _min, .div_max = _max, \
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.div_table = { __VA_ARGS__ } }
88-
#define D_UGATE(_idx, _n, _src, _g, _g1, _r1, _g2, _r2) \
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{ .type = K_DUALGATE, .index = R9A06G032_##_idx, \
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.source = 1 + R9A06G032_##_src, .name = _n, \
91-
.dual = { .group = _g, \
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.g1 = _g1, .r1 = _r1, .g2 = _g2, .r2 = _r2 }, }
93-
94-
enum { K_GATE = 0, K_FFC, K_DIV, K_BITSEL, K_DUALGATE };
72+
#define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) { \
73+
.gate = _clk, \
74+
.reset = _rst, \
75+
.ready = _rdy, \
76+
.midle = _midle, \
77+
.scon = _scon, \
78+
.mirack = _mirack, \
79+
.mistat = _mistat \
80+
}
81+
#define D_GATE(_idx, _n, _src, ...) { \
82+
.type = K_GATE, \
83+
.index = R9A06G032_##_idx, \
84+
.source = 1 + R9A06G032_##_src, \
85+
.name = _n, \
86+
.gate = I_GATE(__VA_ARGS__) \
87+
}
88+
#define D_MODULE(_idx, _n, _src, ...) { \
89+
.type = K_GATE, \
90+
.index = R9A06G032_##_idx, \
91+
.source = 1 + R9A06G032_##_src, \
92+
.name = _n, \
93+
.managed = 1, \
94+
.gate = I_GATE(__VA_ARGS__) \
95+
}
96+
#define D_ROOT(_idx, _n, _mul, _div) { \
97+
.type = K_FFC, \
98+
.index = R9A06G032_##_idx, \
99+
.name = _n, \
100+
.div = _div, \
101+
.mul = _mul \
102+
}
103+
#define D_FFC(_idx, _n, _src, _div) { \
104+
.type = K_FFC, \
105+
.index = R9A06G032_##_idx, \
106+
.source = 1 + R9A06G032_##_src, \
107+
.name = _n, \
108+
.div = _div, \
109+
.mul = 1 \
110+
}
111+
#define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) { \
112+
.type = K_DIV, \
113+
.index = R9A06G032_##_idx, \
114+
.source = 1 + R9A06G032_##_src, \
115+
.name = _n, \
116+
.reg = _reg, \
117+
.div_min = _min, \
118+
.div_max = _max, \
119+
.div_table = { __VA_ARGS__ } \
120+
}
121+
#define D_UGATE(_idx, _n, _src, _g, _g1, _r1, _g2, _r2) { \
122+
.type = K_DUALGATE, \
123+
.index = R9A06G032_##_idx, \
124+
.source = 1 + R9A06G032_##_src, \
125+
.name = _n, \
126+
.dual = { \
127+
.group = _g, \
128+
.g1 = _g1, \
129+
.r1 = _r1, \
130+
.g2 = _g2, \
131+
.r2 = _r2 \
132+
}, \
133+
}
95134

96135
/* Internal clock IDs */
97136
#define R9A06G032_CLKOUT 0

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