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ChristianKoenigAMDalexdeucher
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drm/amdgpu: stop touching sched.ready in the backend
This unfortunately comes up in regular intervals and breaks GPU reset for the engine in question. The sched.ready flag controls if an engine can't get working during hw_init, but should never be set to false during hw_fini. v2: squash in unused variable fix (Alex) Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1 parent 9c2876d commit a2b4785

4 files changed

Lines changed: 1 addition & 16 deletions

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drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c

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Original file line numberDiff line numberDiff line change
@@ -198,8 +198,6 @@ static int jpeg_v2_5_hw_fini(void *handle)
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if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
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RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS))
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jpeg_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
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ring->sched.ready = false;
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}
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return 0;

drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c

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@@ -166,8 +166,6 @@ static int jpeg_v3_0_hw_fini(void *handle)
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RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
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jpeg_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
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ring->sched.ready = false;
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return 0;
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}
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drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

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Original file line numberDiff line numberDiff line change
@@ -497,11 +497,6 @@ static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev)
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ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
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WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
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}
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sdma0->sched.ready = false;
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sdma1->sched.ready = false;
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sdma2->sched.ready = false;
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sdma3->sched.ready = false;
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}
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/**

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

Lines changed: 1 addition & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -373,7 +373,7 @@ static int vcn_v3_0_hw_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct amdgpu_ring *ring;
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int i, j;
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int i;
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for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
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if (adev->vcn.harvest_config & (1 << i))
@@ -388,12 +388,6 @@ static int vcn_v3_0_hw_fini(void *handle)
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vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
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}
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}
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ring->sched.ready = false;
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for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
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ring = &adev->vcn.inst[i].ring_enc[j];
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ring->sched.ready = false;
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}
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}
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return 0;

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