Skip to content

Commit a4366b5

Browse files
nfrapradombgg
authored andcommitted
arm64: dts: mediatek: mt8192: Fix CPUs capacity-dmips-mhz
The capacity-dmips-mhz parameter was miscalculated: this SoC runs the first (Cortex-A55) cluster at a maximum of 2000MHz and the second (Cortex-A76) cluster at a maximum of 2200MHz. In order to calculate the right capacity-dmips-mhz, the following test was performed: 1. CPUFREQ governor was set to 'performance' on both clusters 2. Ran dhrystone with 500000000 iterations for 10 times on each cluster 3. Calculated the mean result for each cluster 4. Calculated DMIPS/MHz: dmips_mhz = dmips_per_second / cpu_mhz 5. Scaled results to 1024: result_c0 = dmips_mhz_c0 / dmips_mhz_c1 * 1024 The mean results for this SoC are: Cluster 0 (LITTLE): 12016411 Dhry/s Cluster 1 (BIG): 31702034 Dhry/s The calculated scaled results are: Cluster 0: 426.953226899238 (rounded to 427) Cluster 1: 1024 Fixes: 4848998 ("arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile") Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230602183515.3778780-1-nfraprado@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
1 parent 6970cad commit a4366b5

1 file changed

Lines changed: 4 additions & 4 deletions

File tree

arch/arm64/boot/dts/mediatek/mt8192.dtsi

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -71,7 +71,7 @@
7171
d-cache-sets = <128>;
7272
next-level-cache = <&l2_0>;
7373
performance-domains = <&performance 0>;
74-
capacity-dmips-mhz = <530>;
74+
capacity-dmips-mhz = <427>;
7575
};
7676

7777
cpu1: cpu@100 {
@@ -89,7 +89,7 @@
8989
d-cache-sets = <128>;
9090
next-level-cache = <&l2_0>;
9191
performance-domains = <&performance 0>;
92-
capacity-dmips-mhz = <530>;
92+
capacity-dmips-mhz = <427>;
9393
};
9494

9595
cpu2: cpu@200 {
@@ -107,7 +107,7 @@
107107
d-cache-sets = <128>;
108108
next-level-cache = <&l2_0>;
109109
performance-domains = <&performance 0>;
110-
capacity-dmips-mhz = <530>;
110+
capacity-dmips-mhz = <427>;
111111
};
112112

113113
cpu3: cpu@300 {
@@ -125,7 +125,7 @@
125125
d-cache-sets = <128>;
126126
next-level-cache = <&l2_0>;
127127
performance-domains = <&performance 0>;
128-
capacity-dmips-mhz = <530>;
128+
capacity-dmips-mhz = <427>;
129129
};
130130

131131
cpu4: cpu@400 {

0 commit comments

Comments
 (0)