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bebarinobebarino
committed
Merge tag 'renesas-clk-for-v6.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven: - Add Expanded Serial Peripheral Interface (xSPI) clocks and resets on Renesas RZ/T21H and RZ/N2H - Add DMAC, interrupt controller (ICU), SPI, and thermal (TSU) clocks and resets on Renesas RZ/V2N - Add more serial (RSCI) clocks and resets on Renesas RZ/V2H and RZ/V2N * tag 'renesas-clk-for-v6.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r9a09g056: Add clock and reset entries for TSU clk: renesas: r9a09g057: Add entries for RSCIs clk: renesas: r9a09g056: Add entries for RSCIs clk: renesas: r9a09g056: Add entries for the RSPIs clk: renesas: r9a09g056: Add entries for ICU clk: renesas: r9a09g056: Add entries for the DMACs clk: renesas: r9a09g077: Propagate rate changes through mux parents clk: renesas: r9a09g077: Add xSPI core and module clocks clk: renesas: rzg2l: Select correct div round macro clk: renesas: rzg2l: Fix intin variable size dt-bindings: clock: renesas,r9a09g077/87: Add XSPI0/1 IDs
2 parents 8f0b4cc + ebb3acf commit a46a9cd

6 files changed

Lines changed: 502 additions & 7 deletions

File tree

‎drivers/clk/renesas/r9a09g056-cpg.c‎

Lines changed: 178 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,11 +46,16 @@ enum clk_ids {
4646
CLK_PLLCLN_DIV2,
4747
CLK_PLLCLN_DIV8,
4848
CLK_PLLCLN_DIV16,
49+
CLK_PLLCLN_DIV64,
50+
CLK_PLLCLN_DIV256,
51+
CLK_PLLCLN_DIV1024,
4952
CLK_PLLDTY_ACPU,
5053
CLK_PLLDTY_ACPU_DIV2,
5154
CLK_PLLDTY_ACPU_DIV4,
5255
CLK_PLLDTY_DIV8,
5356
CLK_PLLDTY_DIV16,
57+
CLK_PLLDTY_RCPU,
58+
CLK_PLLDTY_RCPU_DIV4,
5459
CLK_PLLVDO_CRU0,
5560
CLK_PLLVDO_CRU1,
5661
CLK_PLLVDO_ISP,
@@ -178,12 +183,17 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
178183
DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
179184
DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
180185
DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
186+
DEF_FIXED(".pllcln_div64", CLK_PLLCLN_DIV64, CLK_PLLCLN, 1, 64),
187+
DEF_FIXED(".pllcln_div256", CLK_PLLCLN_DIV256, CLK_PLLCLN, 1, 256),
188+
DEF_FIXED(".pllcln_div1024", CLK_PLLCLN_DIV1024, CLK_PLLCLN, 1, 1024),
181189

182190
DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
183191
DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
184192
DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
185193
DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
186194
DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
195+
DEF_DDIV(".plldty_rcpu", CLK_PLLDTY_RCPU, CLK_PLLDTY, CDDIV3_DIVCTL2, dtable_2_64),
196+
DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4),
187197

188198
DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
189199
DEF_DDIV(".pllvdo_cru1", CLK_PLLVDO_CRU1, CLK_PLLVDO, CDDIV4_DIVCTL0, dtable_2_4),
@@ -231,6 +241,18 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
231241
};
232242

233243
static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
244+
DEF_MOD("dmac_0_aclk", CLK_PLLCM33_GEAR, 0, 0, 0, 0,
245+
BUS_MSTOP(5, BIT(9))),
246+
DEF_MOD("dmac_1_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 1, 0, 1,
247+
BUS_MSTOP(3, BIT(2))),
248+
DEF_MOD("dmac_2_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 2, 0, 2,
249+
BUS_MSTOP(3, BIT(3))),
250+
DEF_MOD("dmac_3_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 3, 0, 3,
251+
BUS_MSTOP(10, BIT(11))),
252+
DEF_MOD("dmac_4_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 4, 0, 4,
253+
BUS_MSTOP(10, BIT(12))),
254+
DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5,
255+
BUS_MSTOP_NONE),
234256
DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
235257
BUS_MSTOP(3, BIT(5))),
236258
DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3,
@@ -265,6 +287,124 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
265287
BUS_MSTOP(5, BIT(13))),
266288
DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
267289
BUS_MSTOP(5, BIT(13))),
290+
DEF_MOD("rsci0_pclk", CLK_PLLCLN_DIV16, 5, 13, 2, 29,
291+
BUS_MSTOP(11, BIT(3))),
292+
DEF_MOD("rsci0_tclk", CLK_PLLCLN_DIV16, 5, 14, 2, 30,
293+
BUS_MSTOP(11, BIT(3))),
294+
DEF_MOD("rsci0_ps_ps3_n", CLK_PLLCLN_DIV1024, 5, 15, 2, 31,
295+
BUS_MSTOP(11, BIT(3))),
296+
DEF_MOD("rsci0_ps_ps2_n", CLK_PLLCLN_DIV256, 6, 0, 3, 0,
297+
BUS_MSTOP(11, BIT(3))),
298+
DEF_MOD("rsci0_ps_ps1_n", CLK_PLLCLN_DIV64, 6, 1, 3, 1,
299+
BUS_MSTOP(11, BIT(3))),
300+
DEF_MOD("rsci1_pclk", CLK_PLLCLN_DIV16, 6, 2, 3, 2,
301+
BUS_MSTOP(11, BIT(4))),
302+
DEF_MOD("rsci1_tclk", CLK_PLLCLN_DIV16, 6, 3, 3, 3,
303+
BUS_MSTOP(11, BIT(4))),
304+
DEF_MOD("rsci1_ps_ps3_n", CLK_PLLCLN_DIV1024, 6, 4, 3, 4,
305+
BUS_MSTOP(11, BIT(4))),
306+
DEF_MOD("rsci1_ps_ps2_n", CLK_PLLCLN_DIV256, 6, 5, 3, 5,
307+
BUS_MSTOP(11, BIT(4))),
308+
DEF_MOD("rsci1_ps_ps1_n", CLK_PLLCLN_DIV64, 6, 6, 3, 6,
309+
BUS_MSTOP(11, BIT(4))),
310+
DEF_MOD("rsci2_pclk", CLK_PLLCLN_DIV16, 6, 7, 3, 7,
311+
BUS_MSTOP(11, BIT(5))),
312+
DEF_MOD("rsci2_tclk", CLK_PLLCLN_DIV16, 6, 8, 3, 8,
313+
BUS_MSTOP(11, BIT(5))),
314+
DEF_MOD("rsci2_ps_ps3_n", CLK_PLLCLN_DIV1024, 6, 9, 3, 9,
315+
BUS_MSTOP(11, BIT(5))),
316+
DEF_MOD("rsci2_ps_ps2_n", CLK_PLLCLN_DIV256, 6, 10, 3, 10,
317+
BUS_MSTOP(11, BIT(5))),
318+
DEF_MOD("rsci2_ps_ps1_n", CLK_PLLCLN_DIV64, 6, 11, 3, 11,
319+
BUS_MSTOP(11, BIT(5))),
320+
DEF_MOD("rsci3_pclk", CLK_PLLCLN_DIV16, 6, 12, 3, 12,
321+
BUS_MSTOP(11, BIT(6))),
322+
DEF_MOD("rsci3_tclk", CLK_PLLCLN_DIV16, 6, 13, 3, 13,
323+
BUS_MSTOP(11, BIT(6))),
324+
DEF_MOD("rsci3_ps_ps3_n", CLK_PLLCLN_DIV1024, 6, 14, 3, 14,
325+
BUS_MSTOP(11, BIT(6))),
326+
DEF_MOD("rsci3_ps_ps2_n", CLK_PLLCLN_DIV256, 6, 15, 3, 15,
327+
BUS_MSTOP(11, BIT(6))),
328+
DEF_MOD("rsci3_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 0, 3, 16,
329+
BUS_MSTOP(11, BIT(6))),
330+
DEF_MOD("rsci4_pclk", CLK_PLLCLN_DIV16, 7, 1, 3, 17,
331+
BUS_MSTOP(11, BIT(7))),
332+
DEF_MOD("rsci4_tclk", CLK_PLLCLN_DIV16, 7, 2, 3, 18,
333+
BUS_MSTOP(11, BIT(7))),
334+
DEF_MOD("rsci4_ps_ps3_n", CLK_PLLCLN_DIV1024, 7, 3, 3, 19,
335+
BUS_MSTOP(11, BIT(7))),
336+
DEF_MOD("rsci4_ps_ps2_n", CLK_PLLCLN_DIV256, 7, 4, 3, 20,
337+
BUS_MSTOP(11, BIT(7))),
338+
DEF_MOD("rsci4_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 5, 3, 21,
339+
BUS_MSTOP(11, BIT(7))),
340+
DEF_MOD("rsci5_pclk", CLK_PLLCLN_DIV16, 7, 6, 3, 22,
341+
BUS_MSTOP(11, BIT(8))),
342+
DEF_MOD("rsci5_tclk", CLK_PLLCLN_DIV16, 7, 7, 3, 23,
343+
BUS_MSTOP(11, BIT(8))),
344+
DEF_MOD("rsci5_ps_ps3_n", CLK_PLLCLN_DIV1024, 7, 8, 3, 24,
345+
BUS_MSTOP(11, BIT(8))),
346+
DEF_MOD("rsci5_ps_ps2_n", CLK_PLLCLN_DIV256, 7, 9, 3, 25,
347+
BUS_MSTOP(11, BIT(8))),
348+
DEF_MOD("rsci5_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 10, 3, 26,
349+
BUS_MSTOP(11, BIT(8))),
350+
DEF_MOD("rsci6_pclk", CLK_PLLCLN_DIV16, 7, 11, 3, 27,
351+
BUS_MSTOP(11, BIT(9))),
352+
DEF_MOD("rsci6_tclk", CLK_PLLCLN_DIV16, 7, 12, 3, 28,
353+
BUS_MSTOP(11, BIT(9))),
354+
DEF_MOD("rsci6_ps_ps3_n", CLK_PLLCLN_DIV1024, 7, 13, 3, 29,
355+
BUS_MSTOP(11, BIT(9))),
356+
DEF_MOD("rsci6_ps_ps2_n", CLK_PLLCLN_DIV256, 7, 14, 3, 30,
357+
BUS_MSTOP(11, BIT(9))),
358+
DEF_MOD("rsci6_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 15, 3, 31,
359+
BUS_MSTOP(11, BIT(9))),
360+
DEF_MOD("rsci7_pclk", CLK_PLLCLN_DIV16, 8, 0, 4, 0,
361+
BUS_MSTOP(11, BIT(10))),
362+
DEF_MOD("rsci7_tclk", CLK_PLLCLN_DIV16, 8, 1, 4, 1,
363+
BUS_MSTOP(11, BIT(10))),
364+
DEF_MOD("rsci7_ps_ps3_n", CLK_PLLCLN_DIV1024, 8, 2, 4, 2,
365+
BUS_MSTOP(11, BIT(10))),
366+
DEF_MOD("rsci7_ps_ps2_n", CLK_PLLCLN_DIV256, 8, 3, 4, 3,
367+
BUS_MSTOP(11, BIT(10))),
368+
DEF_MOD("rsci7_ps_ps1_n", CLK_PLLCLN_DIV64, 8, 4, 4, 4,
369+
BUS_MSTOP(11, BIT(10))),
370+
DEF_MOD("rsci8_pclk", CLK_PLLCLN_DIV16, 8, 5, 4, 5,
371+
BUS_MSTOP(11, BIT(11))),
372+
DEF_MOD("rsci8_tclk", CLK_PLLCLN_DIV16, 8, 6, 4, 6,
373+
BUS_MSTOP(11, BIT(11))),
374+
DEF_MOD("rsci8_ps_ps3_n", CLK_PLLCLN_DIV1024, 8, 7, 4, 7,
375+
BUS_MSTOP(11, BIT(11))),
376+
DEF_MOD("rsci8_ps_ps2_n", CLK_PLLCLN_DIV256, 8, 8, 4, 8,
377+
BUS_MSTOP(11, BIT(11))),
378+
DEF_MOD("rsci8_ps_ps1_n", CLK_PLLCLN_DIV64, 8, 9, 4, 9,
379+
BUS_MSTOP(11, BIT(11))),
380+
DEF_MOD("rsci9_pclk", CLK_PLLCLN_DIV16, 8, 10, 4, 10,
381+
BUS_MSTOP(11, BIT(12))),
382+
DEF_MOD("rsci9_tclk", CLK_PLLCLN_DIV16, 8, 11, 4, 11,
383+
BUS_MSTOP(11, BIT(12))),
384+
DEF_MOD("rsci9_ps_ps3_n", CLK_PLLCLN_DIV1024, 8, 12, 4, 12,
385+
BUS_MSTOP(11, BIT(12))),
386+
DEF_MOD("rsci9_ps_ps2_n", CLK_PLLCLN_DIV256, 8, 13, 4, 13,
387+
BUS_MSTOP(11, BIT(12))),
388+
DEF_MOD("rsci9_ps_ps1_n", CLK_PLLCLN_DIV64, 8, 14, 4, 14,
389+
BUS_MSTOP(11, BIT(12))),
390+
DEF_MOD("rspi_0_pclk", CLK_PLLCLN_DIV8, 5, 4, 2, 20,
391+
BUS_MSTOP(11, BIT(0))),
392+
DEF_MOD("rspi_0_pclk_sfr", CLK_PLLCLN_DIV8, 5, 5, 2, 21,
393+
BUS_MSTOP(11, BIT(0))),
394+
DEF_MOD("rspi_0_tclk", CLK_PLLCLN_DIV8, 5, 6, 2, 22,
395+
BUS_MSTOP(11, BIT(0))),
396+
DEF_MOD("rspi_1_pclk", CLK_PLLCLN_DIV8, 5, 7, 2, 23,
397+
BUS_MSTOP(11, BIT(1))),
398+
DEF_MOD("rspi_1_pclk_sfr", CLK_PLLCLN_DIV8, 5, 8, 2, 24,
399+
BUS_MSTOP(11, BIT(1))),
400+
DEF_MOD("rspi_1_tclk", CLK_PLLCLN_DIV8, 5, 9, 2, 25,
401+
BUS_MSTOP(11, BIT(1))),
402+
DEF_MOD("rspi_2_pclk", CLK_PLLCLN_DIV8, 5, 10, 2, 26,
403+
BUS_MSTOP(11, BIT(2))),
404+
DEF_MOD("rspi_2_pclk_sfr", CLK_PLLCLN_DIV8, 5, 11, 2, 27,
405+
BUS_MSTOP(11, BIT(2))),
406+
DEF_MOD("rspi_2_tclk", CLK_PLLCLN_DIV8, 5, 12, 2, 28,
407+
BUS_MSTOP(11, BIT(2))),
268408
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
269409
BUS_MSTOP(3, BIT(14))),
270410
DEF_MOD("i3c_0_pclkrw", CLK_PLLCLN_DIV16, 9, 0, 4, 16,
@@ -397,10 +537,20 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
397537
BUS_MSTOP(3, BIT(4))),
398538
DEF_MOD("gpu_0_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,
399539
BUS_MSTOP(3, BIT(4))),
540+
DEF_MOD("tsu_0_pclk", CLK_QEXTAL, 16, 9, 8, 9,
541+
BUS_MSTOP(5, BIT(2))),
542+
DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10,
543+
BUS_MSTOP(2, BIT(15))),
400544
};
401545

402546
static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
403547
DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
548+
DEF_RST(3, 1, 1, 2), /* DMAC_0_ARESETN */
549+
DEF_RST(3, 2, 1, 3), /* DMAC_1_ARESETN */
550+
DEF_RST(3, 3, 1, 4), /* DMAC_2_ARESETN */
551+
DEF_RST(3, 4, 1, 5), /* DMAC_3_ARESETN */
552+
DEF_RST(3, 5, 1, 6), /* DMAC_4_ARESETN */
553+
DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */
404554
DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
405555
DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
406556
DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */
@@ -415,6 +565,32 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
415565
DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
416566
DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
417567
DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
568+
DEF_RST(8, 1, 3, 18), /* RSCI0_PRESETN */
569+
DEF_RST(8, 2, 3, 19), /* RSCI0_TRESETN */
570+
DEF_RST(8, 3, 3, 20), /* RSCI1_PRESETN */
571+
DEF_RST(8, 4, 3, 21), /* RSCI1_TRESETN */
572+
DEF_RST(8, 5, 3, 22), /* RSCI2_PRESETN */
573+
DEF_RST(8, 6, 3, 23), /* RSCI2_TRESETN */
574+
DEF_RST(8, 7, 3, 24), /* RSCI3_PRESETN */
575+
DEF_RST(8, 8, 3, 25), /* RSCI3_TRESETN */
576+
DEF_RST(8, 9, 3, 26), /* RSCI4_PRESETN */
577+
DEF_RST(8, 10, 3, 27), /* RSCI4_TRESETN */
578+
DEF_RST(8, 11, 3, 28), /* RSCI5_PRESETN */
579+
DEF_RST(8, 12, 3, 29), /* RSCI5_TRESETN */
580+
DEF_RST(8, 13, 3, 30), /* RSCI6_PRESETN */
581+
DEF_RST(8, 14, 3, 31), /* RSCI6_TRESETN */
582+
DEF_RST(8, 15, 4, 0), /* RSCI7_PRESETN */
583+
DEF_RST(9, 0, 4, 1), /* RSCI7_TRESETN */
584+
DEF_RST(9, 1, 4, 2), /* RSCI8_PRESETN */
585+
DEF_RST(9, 2, 4, 3), /* RSCI8_TRESETN */
586+
DEF_RST(9, 3, 4, 4), /* RSCI9_PRESETN */
587+
DEF_RST(9, 4, 4, 5), /* RSCI9_TRESETN */
588+
DEF_RST(7, 11, 3, 12), /* RSPI_0_PRESETN */
589+
DEF_RST(7, 12, 3, 13), /* RSPI_0_TRESETN */
590+
DEF_RST(7, 13, 3, 14), /* RSPI_1_PRESETN */
591+
DEF_RST(7, 14, 3, 15), /* RSPI_1_TRESETN */
592+
DEF_RST(7, 15, 3, 16), /* RSPI_2_PRESETN */
593+
DEF_RST(8, 0, 3, 17), /* RSPI_2_TRESETN */
418594
DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
419595
DEF_RST(9, 6, 4, 7), /* I3C_0_PRESETN */
420596
DEF_RST(9, 7, 4, 8), /* I3C_0_TRESETN */
@@ -454,6 +630,8 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
454630
DEF_RST(13, 13, 6, 14), /* GPU_0_RESETN */
455631
DEF_RST(13, 14, 6, 15), /* GPU_0_AXI_RESETN */
456632
DEF_RST(13, 15, 6, 16), /* GPU_0_ACE_RESETN */
633+
DEF_RST(15, 7, 7, 8), /* TSU_0_PRESETN */
634+
DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */
457635
};
458636

459637
const struct rzv2h_cpg_info r9a09g056_cpg_info __initconst = {

‎drivers/clk/renesas/r9a09g057-cpg.c‎

Lines changed: 126 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,9 @@ enum clk_ids {
4646
CLK_PLLCLN_DIV2,
4747
CLK_PLLCLN_DIV8,
4848
CLK_PLLCLN_DIV16,
49+
CLK_PLLCLN_DIV64,
50+
CLK_PLLCLN_DIV256,
51+
CLK_PLLCLN_DIV1024,
4952
CLK_PLLDTY_ACPU,
5053
CLK_PLLDTY_ACPU_DIV2,
5154
CLK_PLLDTY_ACPU_DIV4,
@@ -182,6 +185,9 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
182185
DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
183186
DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
184187
DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
188+
DEF_FIXED(".pllcln_div64", CLK_PLLCLN_DIV64, CLK_PLLCLN, 1, 64),
189+
DEF_FIXED(".pllcln_div256", CLK_PLLCLN_DIV256, CLK_PLLCLN, 1, 256),
190+
DEF_FIXED(".pllcln_div1024", CLK_PLLCLN_DIV1024, CLK_PLLCLN, 1, 1024),
185191

186192
DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
187193
DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
@@ -288,6 +294,106 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
288294
BUS_MSTOP(5, BIT(13))),
289295
DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
290296
BUS_MSTOP(5, BIT(13))),
297+
DEF_MOD("rsci0_pclk", CLK_PLLCLN_DIV16, 5, 13, 2, 29,
298+
BUS_MSTOP(11, BIT(3))),
299+
DEF_MOD("rsci0_tclk", CLK_PLLCLN_DIV16, 5, 14, 2, 30,
300+
BUS_MSTOP(11, BIT(3))),
301+
DEF_MOD("rsci0_ps_ps3_n", CLK_PLLCLN_DIV1024, 5, 15, 2, 31,
302+
BUS_MSTOP(11, BIT(3))),
303+
DEF_MOD("rsci0_ps_ps2_n", CLK_PLLCLN_DIV256, 6, 0, 3, 0,
304+
BUS_MSTOP(11, BIT(3))),
305+
DEF_MOD("rsci0_ps_ps1_n", CLK_PLLCLN_DIV64, 6, 1, 3, 1,
306+
BUS_MSTOP(11, BIT(3))),
307+
DEF_MOD("rsci1_pclk", CLK_PLLCLN_DIV16, 6, 2, 3, 2,
308+
BUS_MSTOP(11, BIT(4))),
309+
DEF_MOD("rsci1_tclk", CLK_PLLCLN_DIV16, 6, 3, 3, 3,
310+
BUS_MSTOP(11, BIT(4))),
311+
DEF_MOD("rsci1_ps_ps3_n", CLK_PLLCLN_DIV1024, 6, 4, 3, 4,
312+
BUS_MSTOP(11, BIT(4))),
313+
DEF_MOD("rsci1_ps_ps2_n", CLK_PLLCLN_DIV256, 6, 5, 3, 5,
314+
BUS_MSTOP(11, BIT(4))),
315+
DEF_MOD("rsci1_ps_ps1_n", CLK_PLLCLN_DIV64, 6, 6, 3, 6,
316+
BUS_MSTOP(11, BIT(4))),
317+
DEF_MOD("rsci2_pclk", CLK_PLLCLN_DIV16, 6, 7, 3, 7,
318+
BUS_MSTOP(11, BIT(5))),
319+
DEF_MOD("rsci2_tclk", CLK_PLLCLN_DIV16, 6, 8, 3, 8,
320+
BUS_MSTOP(11, BIT(5))),
321+
DEF_MOD("rsci2_ps_ps3_n", CLK_PLLCLN_DIV1024, 6, 9, 3, 9,
322+
BUS_MSTOP(11, BIT(5))),
323+
DEF_MOD("rsci2_ps_ps2_n", CLK_PLLCLN_DIV256, 6, 10, 3, 10,
324+
BUS_MSTOP(11, BIT(5))),
325+
DEF_MOD("rsci2_ps_ps1_n", CLK_PLLCLN_DIV64, 6, 11, 3, 11,
326+
BUS_MSTOP(11, BIT(5))),
327+
DEF_MOD("rsci3_pclk", CLK_PLLCLN_DIV16, 6, 12, 3, 12,
328+
BUS_MSTOP(11, BIT(6))),
329+
DEF_MOD("rsci3_tclk", CLK_PLLCLN_DIV16, 6, 13, 3, 13,
330+
BUS_MSTOP(11, BIT(6))),
331+
DEF_MOD("rsci3_ps_ps3_n", CLK_PLLCLN_DIV1024, 6, 14, 3, 14,
332+
BUS_MSTOP(11, BIT(6))),
333+
DEF_MOD("rsci3_ps_ps2_n", CLK_PLLCLN_DIV256, 6, 15, 3, 15,
334+
BUS_MSTOP(11, BIT(6))),
335+
DEF_MOD("rsci3_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 0, 3, 16,
336+
BUS_MSTOP(11, BIT(6))),
337+
DEF_MOD("rsci4_pclk", CLK_PLLCLN_DIV16, 7, 1, 3, 17,
338+
BUS_MSTOP(11, BIT(7))),
339+
DEF_MOD("rsci4_tclk", CLK_PLLCLN_DIV16, 7, 2, 3, 18,
340+
BUS_MSTOP(11, BIT(7))),
341+
DEF_MOD("rsci4_ps_ps3_n", CLK_PLLCLN_DIV1024, 7, 3, 3, 19,
342+
BUS_MSTOP(11, BIT(7))),
343+
DEF_MOD("rsci4_ps_ps2_n", CLK_PLLCLN_DIV256, 7, 4, 3, 20,
344+
BUS_MSTOP(11, BIT(7))),
345+
DEF_MOD("rsci4_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 5, 3, 21,
346+
BUS_MSTOP(11, BIT(7))),
347+
DEF_MOD("rsci5_pclk", CLK_PLLCLN_DIV16, 7, 6, 3, 22,
348+
BUS_MSTOP(11, BIT(8))),
349+
DEF_MOD("rsci5_tclk", CLK_PLLCLN_DIV16, 7, 7, 3, 23,
350+
BUS_MSTOP(11, BIT(8))),
351+
DEF_MOD("rsci5_ps_ps3_n", CLK_PLLCLN_DIV1024, 7, 8, 3, 24,
352+
BUS_MSTOP(11, BIT(8))),
353+
DEF_MOD("rsci5_ps_ps2_n", CLK_PLLCLN_DIV256, 7, 9, 3, 25,
354+
BUS_MSTOP(11, BIT(8))),
355+
DEF_MOD("rsci5_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 10, 3, 26,
356+
BUS_MSTOP(11, BIT(8))),
357+
DEF_MOD("rsci6_pclk", CLK_PLLCLN_DIV16, 7, 11, 3, 27,
358+
BUS_MSTOP(11, BIT(9))),
359+
DEF_MOD("rsci6_tclk", CLK_PLLCLN_DIV16, 7, 12, 3, 28,
360+
BUS_MSTOP(11, BIT(9))),
361+
DEF_MOD("rsci6_ps_ps3_n", CLK_PLLCLN_DIV1024, 7, 13, 3, 29,
362+
BUS_MSTOP(11, BIT(9))),
363+
DEF_MOD("rsci6_ps_ps2_n", CLK_PLLCLN_DIV256, 7, 14, 3, 30,
364+
BUS_MSTOP(11, BIT(9))),
365+
DEF_MOD("rsci6_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 15, 3, 31,
366+
BUS_MSTOP(11, BIT(9))),
367+
DEF_MOD("rsci7_pclk", CLK_PLLCLN_DIV16, 8, 0, 4, 0,
368+
BUS_MSTOP(11, BIT(10))),
369+
DEF_MOD("rsci7_tclk", CLK_PLLCLN_DIV16, 8, 1, 4, 1,
370+
BUS_MSTOP(11, BIT(10))),
371+
DEF_MOD("rsci7_ps_ps3_n", CLK_PLLCLN_DIV1024, 8, 2, 4, 2,
372+
BUS_MSTOP(11, BIT(10))),
373+
DEF_MOD("rsci7_ps_ps2_n", CLK_PLLCLN_DIV256, 8, 3, 4, 3,
374+
BUS_MSTOP(11, BIT(10))),
375+
DEF_MOD("rsci7_ps_ps1_n", CLK_PLLCLN_DIV64, 8, 4, 4, 4,
376+
BUS_MSTOP(11, BIT(10))),
377+
DEF_MOD("rsci8_pclk", CLK_PLLCLN_DIV16, 8, 5, 4, 5,
378+
BUS_MSTOP(11, BIT(11))),
379+
DEF_MOD("rsci8_tclk", CLK_PLLCLN_DIV16, 8, 6, 4, 6,
380+
BUS_MSTOP(11, BIT(11))),
381+
DEF_MOD("rsci8_ps_ps3_n", CLK_PLLCLN_DIV1024, 8, 7, 4, 7,
382+
BUS_MSTOP(11, BIT(11))),
383+
DEF_MOD("rsci8_ps_ps2_n", CLK_PLLCLN_DIV256, 8, 8, 4, 8,
384+
BUS_MSTOP(11, BIT(11))),
385+
DEF_MOD("rsci8_ps_ps1_n", CLK_PLLCLN_DIV64, 8, 9, 4, 9,
386+
BUS_MSTOP(11, BIT(11))),
387+
DEF_MOD("rsci9_pclk", CLK_PLLCLN_DIV16, 8, 10, 4, 10,
388+
BUS_MSTOP(11, BIT(12))),
389+
DEF_MOD("rsci9_tclk", CLK_PLLCLN_DIV16, 8, 11, 4, 11,
390+
BUS_MSTOP(11, BIT(12))),
391+
DEF_MOD("rsci9_ps_ps3_n", CLK_PLLCLN_DIV1024, 8, 12, 4, 12,
392+
BUS_MSTOP(11, BIT(12))),
393+
DEF_MOD("rsci9_ps_ps2_n", CLK_PLLCLN_DIV256, 8, 13, 4, 13,
394+
BUS_MSTOP(11, BIT(12))),
395+
DEF_MOD("rsci9_ps_ps1_n", CLK_PLLCLN_DIV64, 8, 14, 4, 14,
396+
BUS_MSTOP(11, BIT(12))),
291397
DEF_MOD("rtc_0_clk_rtc", CLK_PLLCM33_DIV16, 5, 3, 2, 19,
292398
BUS_MSTOP(3, BIT(11) | BIT(12))),
293399
DEF_MOD("rspi_0_pclk", CLK_PLLCLN_DIV8, 5, 4, 2, 20,
@@ -488,6 +594,26 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
488594
DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
489595
DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
490596
DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
597+
DEF_RST(8, 1, 3, 18), /* RSCI0_PRESETN */
598+
DEF_RST(8, 2, 3, 19), /* RSCI0_TRESETN */
599+
DEF_RST(8, 3, 3, 20), /* RSCI1_PRESETN */
600+
DEF_RST(8, 4, 3, 21), /* RSCI1_TRESETN */
601+
DEF_RST(8, 5, 3, 22), /* RSCI2_PRESETN */
602+
DEF_RST(8, 6, 3, 23), /* RSCI2_TRESETN */
603+
DEF_RST(8, 7, 3, 24), /* RSCI3_PRESETN */
604+
DEF_RST(8, 8, 3, 25), /* RSCI3_TRESETN */
605+
DEF_RST(8, 9, 3, 26), /* RSCI4_PRESETN */
606+
DEF_RST(8, 10, 3, 27), /* RSCI4_TRESETN */
607+
DEF_RST(8, 11, 3, 28), /* RSCI5_PRESETN */
608+
DEF_RST(8, 12, 3, 29), /* RSCI5_TRESETN */
609+
DEF_RST(8, 13, 3, 30), /* RSCI6_PRESETN */
610+
DEF_RST(8, 14, 3, 31), /* RSCI6_TRESETN */
611+
DEF_RST(8, 15, 4, 0), /* RSCI7_PRESETN */
612+
DEF_RST(9, 0, 4, 1), /* RSCI7_TRESETN */
613+
DEF_RST(9, 1, 4, 2), /* RSCI8_PRESETN */
614+
DEF_RST(9, 2, 4, 3), /* RSCI8_TRESETN */
615+
DEF_RST(9, 3, 4, 4), /* RSCI9_PRESETN */
616+
DEF_RST(9, 4, 4, 5), /* RSCI9_TRESETN */
491617
DEF_RST(7, 9, 3, 10), /* RTC_0_RST_RTC */
492618
DEF_RST(7, 10, 3, 11), /* RTC_0_RST_RTC_V */
493619
DEF_RST(7, 11, 3, 12), /* RSPI_0_PRESETN */

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