@@ -54,7 +54,7 @@ static void iavf_unmap_and_free_tx_resource(struct iavf_ring *ring,
5454 * iavf_clean_tx_ring - Free any empty Tx buffers
5555 * @tx_ring: ring to be cleaned
5656 **/
57- void iavf_clean_tx_ring (struct iavf_ring * tx_ring )
57+ static void iavf_clean_tx_ring (struct iavf_ring * tx_ring )
5858{
5959 unsigned long bi_size ;
6060 u16 i ;
@@ -110,7 +110,7 @@ void iavf_free_tx_resources(struct iavf_ring *tx_ring)
110110 * Since there is no access to the ring head register
111111 * in XL710, we need to use our local copies
112112 **/
113- u32 iavf_get_tx_pending (struct iavf_ring * ring , bool in_sw )
113+ static u32 iavf_get_tx_pending (struct iavf_ring * ring , bool in_sw )
114114{
115115 u32 head , tail ;
116116
@@ -127,6 +127,24 @@ u32 iavf_get_tx_pending(struct iavf_ring *ring, bool in_sw)
127127 return 0 ;
128128}
129129
130+ /**
131+ * iavf_force_wb - Issue SW Interrupt so HW does a wb
132+ * @vsi: the VSI we care about
133+ * @q_vector: the vector on which to force writeback
134+ **/
135+ static void iavf_force_wb (struct iavf_vsi * vsi , struct iavf_q_vector * q_vector )
136+ {
137+ u32 val = IAVF_VFINT_DYN_CTLN1_INTENA_MASK |
138+ IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */
139+ IAVF_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |
140+ IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK
141+ /* allow 00 to be written to the index */ ;
142+
143+ wr32 (& vsi -> back -> hw ,
144+ IAVF_VFINT_DYN_CTLN1 (q_vector -> reg_idx ),
145+ val );
146+ }
147+
130148/**
131149 * iavf_detect_recover_hung - Function to detect and recover hung_queues
132150 * @vsi: pointer to vsi struct with tx queues
@@ -352,25 +370,6 @@ static void iavf_enable_wb_on_itr(struct iavf_vsi *vsi,
352370 q_vector -> arm_wb_state = true;
353371}
354372
355- /**
356- * iavf_force_wb - Issue SW Interrupt so HW does a wb
357- * @vsi: the VSI we care about
358- * @q_vector: the vector on which to force writeback
359- *
360- **/
361- void iavf_force_wb (struct iavf_vsi * vsi , struct iavf_q_vector * q_vector )
362- {
363- u32 val = IAVF_VFINT_DYN_CTLN1_INTENA_MASK |
364- IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */
365- IAVF_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |
366- IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK
367- /* allow 00 to be written to the index */ ;
368-
369- wr32 (& vsi -> back -> hw ,
370- IAVF_VFINT_DYN_CTLN1 (q_vector -> reg_idx ),
371- val );
372- }
373-
374373static inline bool iavf_container_is_rx (struct iavf_q_vector * q_vector ,
375374 struct iavf_ring_container * rc )
376375{
@@ -687,7 +686,7 @@ int iavf_setup_tx_descriptors(struct iavf_ring *tx_ring)
687686 * iavf_clean_rx_ring - Free Rx buffers
688687 * @rx_ring: ring to be cleaned
689688 **/
690- void iavf_clean_rx_ring (struct iavf_ring * rx_ring )
689+ static void iavf_clean_rx_ring (struct iavf_ring * rx_ring )
691690{
692691 unsigned long bi_size ;
693692 u16 i ;
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