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krzkkwilczynski
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dt-bindings: PCI: socionext,uniphier-pcie-ep: Add top-level constraints
Properties with variable number of items per each device are expected to have widest constraints in top-level "properties:" block and further customized (narrowed) in "if:then:". Add missing top-level constraints for clock-names and reset-names. Link: https://lore.kernel.org/linux-pci/20240818172843.121787-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
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Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml

Lines changed: 6 additions & 2 deletions
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@@ -38,13 +38,17 @@ properties:
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minItems: 1
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maxItems: 2
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clock-names: true
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clock-names:
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minItems: 1
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maxItems: 2
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resets:
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minItems: 1
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maxItems: 2
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reset-names: true
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reset-names:
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minItems: 1
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maxItems: 2
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num-ib-windows:
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const: 16

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