|
14 | 14 | stdout-path = &uart1; |
15 | 15 | }; |
16 | 16 |
|
17 | | - regulators { |
18 | | - compatible = "simple-bus"; |
19 | | - #address-cells = <1>; |
20 | | - #size-cells = <0>; |
21 | | - |
22 | | - reg_fec_phy: regulator@0 { |
23 | | - compatible = "regulator-fixed"; |
24 | | - reg = <0>; |
25 | | - regulator-name = "fec-phy"; |
26 | | - regulator-min-microvolt = <3300000>; |
27 | | - regulator-max-microvolt = <3300000>; |
28 | | - gpio = <&gpio4 9 0>; |
29 | | - enable-active-high; |
30 | | - }; |
| 17 | + reg_fec_phy: regulator-0 { |
| 18 | + compatible = "regulator-fixed"; |
| 19 | + regulator-name = "fec-phy"; |
| 20 | + regulator-min-microvolt = <3300000>; |
| 21 | + regulator-max-microvolt = <3300000>; |
| 22 | + gpio = <&gpio4 9 0>; |
| 23 | + enable-active-high; |
31 | 24 | }; |
32 | 25 |
|
33 | 26 | memory@80000000 { |
|
39 | 32 | &iomuxc { |
40 | 33 | pinctrl_uart1: uart1grp { |
41 | 34 | fsl,pins = < |
42 | | - MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 |
43 | | - MX25_PAD_UART1_RXD__UART1_RXD 0x80000000 |
44 | | - MX25_PAD_UART1_CTS__UART1_CTS 0x80000000 |
45 | | - MX25_PAD_UART1_RTS__UART1_RTS 0x80000000 |
| 35 | + MX25_PAD_UART1_TXD__UART1_TXD 0x00000020 |
| 36 | + MX25_PAD_UART1_RXD__UART1_RXD 0x000000a0 |
| 37 | + MX25_PAD_UART1_CTS__UART1_CTS 0x00000060 |
| 38 | + MX25_PAD_UART1_RTS__UART1_RTS 0x000000e0 |
46 | 39 | >; |
47 | 40 | }; |
48 | 41 |
|
49 | 42 | pinctrl_fec: fecgrp { |
50 | 43 | fsl,pins = < |
51 | | - MX25_PAD_D11__GPIO_4_9 0x80000000 /* FEC PHY power on pin */ |
52 | | - MX25_PAD_D13__GPIO_4_7 0x80000000 /* FEC reset */ |
53 | | - MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 |
54 | | - MX25_PAD_FEC_MDIO__FEC_MDIO 0x80000000 |
55 | | - MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 |
56 | | - MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 |
57 | | - MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 |
58 | | - MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 |
59 | | - MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 |
60 | | - MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 |
61 | | - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000 |
| 44 | + MX25_PAD_D11__GPIO_4_9 0x00000021 /* FEC PHY power on pin */ |
| 45 | + MX25_PAD_D13__GPIO_4_7 0x000000a1 /* FEC reset */ |
| 46 | + MX25_PAD_FEC_MDC__FEC_MDC 0x00000060 |
| 47 | + MX25_PAD_FEC_MDIO__FEC_MDIO 0x000001f0 |
| 48 | + MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x00000060 |
| 49 | + MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x00000060 |
| 50 | + MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x00000060 |
| 51 | + MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x000000c1 |
| 52 | + MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x000000c0 |
| 53 | + MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x000000c0 |
| 54 | + MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x000000c0 |
62 | 55 | >; |
63 | 56 | }; |
64 | 57 |
|
65 | 58 | pinctrl_nfc: nfcgrp { |
66 | 59 | fsl,pins = < |
67 | | - MX25_PAD_NF_CE0__NF_CE0 0x80000000 |
| 60 | + MX25_PAD_NF_CE0__NF_CE0 0x00000001 |
68 | 61 | MX25_PAD_NFWE_B__NFWE_B 0x80000000 |
69 | 62 | MX25_PAD_NFRE_B__NFRE_B 0x80000000 |
70 | 63 | MX25_PAD_NFALE__NFALE 0x80000000 |
71 | 64 | MX25_PAD_NFCLE__NFCLE 0x80000000 |
72 | 65 | MX25_PAD_NFWP_B__NFWP_B 0x80000000 |
73 | | - MX25_PAD_NFRB__NFRB 0x80000000 |
74 | | - MX25_PAD_D7__D7 0x80000000 |
75 | | - MX25_PAD_D6__D6 0x80000000 |
76 | | - MX25_PAD_D5__D5 0x80000000 |
77 | | - MX25_PAD_D4__D4 0x80000000 |
78 | | - MX25_PAD_D3__D3 0x80000000 |
79 | | - MX25_PAD_D2__D2 0x80000000 |
80 | | - MX25_PAD_D1__D1 0x80000000 |
81 | | - MX25_PAD_D0__D0 0x80000000 |
| 66 | + MX25_PAD_NFRB__NFRB 0x000000e0 |
| 67 | + MX25_PAD_D7__D7 0x00000080 |
| 68 | + MX25_PAD_D6__D6 0x00000080 |
| 69 | + MX25_PAD_D5__D5 0x00000080 |
| 70 | + MX25_PAD_D4__D4 0x00000080 |
| 71 | + MX25_PAD_D3__D3 0x00000080 |
| 72 | + MX25_PAD_D2__D2 0x00000080 |
| 73 | + MX25_PAD_D1__D1 0x00000000 |
| 74 | + MX25_PAD_D0__D0 0x00000080 |
82 | 75 | >; |
83 | 76 | }; |
84 | 77 | }; |
|
0 commit comments