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clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parents
Use ARRAY_SIZE for num_parents instead of hardcoding the value. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Tested-by: Jonathan McDowell <noodles@earth.li> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220226135235.10051-7-ansuelsmth@gmail.com
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Lines changed: 34 additions & 34 deletions

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‎drivers/clk/qcom/gcc-ipq806x.c‎

Lines changed: 34 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -373,7 +373,7 @@ static struct clk_rcg gsbi1_uart_src = {
373373
.hw.init = &(struct clk_init_data){
374374
.name = "gsbi1_uart_src",
375375
.parent_data = gcc_pxo_pll8,
376-
.num_parents = 2,
376+
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
377377
.ops = &clk_rcg_ops,
378378
.flags = CLK_SET_PARENT_GATE,
379379
},
@@ -424,7 +424,7 @@ static struct clk_rcg gsbi2_uart_src = {
424424
.hw.init = &(struct clk_init_data){
425425
.name = "gsbi2_uart_src",
426426
.parent_data = gcc_pxo_pll8,
427-
.num_parents = 2,
427+
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
428428
.ops = &clk_rcg_ops,
429429
.flags = CLK_SET_PARENT_GATE,
430430
},
@@ -475,7 +475,7 @@ static struct clk_rcg gsbi4_uart_src = {
475475
.hw.init = &(struct clk_init_data){
476476
.name = "gsbi4_uart_src",
477477
.parent_data = gcc_pxo_pll8,
478-
.num_parents = 2,
478+
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
479479
.ops = &clk_rcg_ops,
480480
.flags = CLK_SET_PARENT_GATE,
481481
},
@@ -526,7 +526,7 @@ static struct clk_rcg gsbi5_uart_src = {
526526
.hw.init = &(struct clk_init_data){
527527
.name = "gsbi5_uart_src",
528528
.parent_data = gcc_pxo_pll8,
529-
.num_parents = 2,
529+
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
530530
.ops = &clk_rcg_ops,
531531
.flags = CLK_SET_PARENT_GATE,
532532
},
@@ -577,7 +577,7 @@ static struct clk_rcg gsbi6_uart_src = {
577577
.hw.init = &(struct clk_init_data){
578578
.name = "gsbi6_uart_src",
579579
.parent_data = gcc_pxo_pll8,
580-
.num_parents = 2,
580+
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
581581
.ops = &clk_rcg_ops,
582582
.flags = CLK_SET_PARENT_GATE,
583583
},
@@ -628,7 +628,7 @@ static struct clk_rcg gsbi7_uart_src = {
628628
.hw.init = &(struct clk_init_data){
629629
.name = "gsbi7_uart_src",
630630
.parent_data = gcc_pxo_pll8,
631-
.num_parents = 2,
631+
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
632632
.ops = &clk_rcg_ops,
633633
.flags = CLK_SET_PARENT_GATE,
634634
},
@@ -692,7 +692,7 @@ static struct clk_rcg gsbi1_qup_src = {
692692
.hw.init = &(struct clk_init_data){
693693
.name = "gsbi1_qup_src",
694694
.parent_data = gcc_pxo_pll8,
695-
.num_parents = 2,
695+
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
696696
.ops = &clk_rcg_ops,
697697
.flags = CLK_SET_PARENT_GATE,
698698
},
@@ -743,7 +743,7 @@ static struct clk_rcg gsbi2_qup_src = {
743743
.hw.init = &(struct clk_init_data){
744744
.name = "gsbi2_qup_src",
745745
.parent_data = gcc_pxo_pll8,
746-
.num_parents = 2,
746+
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
747747
.ops = &clk_rcg_ops,
748748
.flags = CLK_SET_PARENT_GATE,
749749
},
@@ -794,7 +794,7 @@ static struct clk_rcg gsbi4_qup_src = {
794794
.hw.init = &(struct clk_init_data){
795795
.name = "gsbi4_qup_src",
796796
.parent_data = gcc_pxo_pll8,
797-
.num_parents = 2,
797+
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
798798
.ops = &clk_rcg_ops,
799799
.flags = CLK_SET_PARENT_GATE,
800800
},
@@ -845,7 +845,7 @@ static struct clk_rcg gsbi5_qup_src = {
845845
.hw.init = &(struct clk_init_data){
846846
.name = "gsbi5_qup_src",
847847
.parent_data = gcc_pxo_pll8,
848-
.num_parents = 2,
848+
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
849849
.ops = &clk_rcg_ops,
850850
.flags = CLK_SET_PARENT_GATE,
851851
},
@@ -896,7 +896,7 @@ static struct clk_rcg gsbi6_qup_src = {
896896
.hw.init = &(struct clk_init_data){
897897
.name = "gsbi6_qup_src",
898898
.parent_data = gcc_pxo_pll8,
899-
.num_parents = 2,
899+
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
900900
.ops = &clk_rcg_ops,
901901
.flags = CLK_SET_PARENT_GATE,
902902
},
@@ -947,7 +947,7 @@ static struct clk_rcg gsbi7_qup_src = {
947947
.hw.init = &(struct clk_init_data){
948948
.name = "gsbi7_qup_src",
949949
.parent_data = gcc_pxo_pll8,
950-
.num_parents = 2,
950+
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
951951
.ops = &clk_rcg_ops,
952952
.flags = CLK_SET_PARENT_GATE,
953953
},
@@ -1099,7 +1099,7 @@ static struct clk_rcg gp0_src = {
10991099
.hw.init = &(struct clk_init_data){
11001100
.name = "gp0_src",
11011101
.parent_data = gcc_pxo_pll8_cxo,
1102-
.num_parents = 3,
1102+
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
11031103
.ops = &clk_rcg_ops,
11041104
.flags = CLK_SET_PARENT_GATE,
11051105
},
@@ -1150,7 +1150,7 @@ static struct clk_rcg gp1_src = {
11501150
.hw.init = &(struct clk_init_data){
11511151
.name = "gp1_src",
11521152
.parent_data = gcc_pxo_pll8_cxo,
1153-
.num_parents = 3,
1153+
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
11541154
.ops = &clk_rcg_ops,
11551155
.flags = CLK_SET_RATE_GATE,
11561156
},
@@ -1201,7 +1201,7 @@ static struct clk_rcg gp2_src = {
12011201
.hw.init = &(struct clk_init_data){
12021202
.name = "gp2_src",
12031203
.parent_data = gcc_pxo_pll8_cxo,
1204-
.num_parents = 3,
1204+
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
12051205
.ops = &clk_rcg_ops,
12061206
.flags = CLK_SET_RATE_GATE,
12071207
},
@@ -1257,7 +1257,7 @@ static struct clk_rcg prng_src = {
12571257
.hw.init = &(struct clk_init_data){
12581258
.name = "prng_src",
12591259
.parent_data = gcc_pxo_pll8,
1260-
.num_parents = 2,
1260+
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
12611261
.ops = &clk_rcg_ops,
12621262
},
12631263
},
@@ -1321,7 +1321,7 @@ static struct clk_rcg sdc1_src = {
13211321
.hw.init = &(struct clk_init_data){
13221322
.name = "sdc1_src",
13231323
.parent_data = gcc_pxo_pll8,
1324-
.num_parents = 2,
1324+
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
13251325
.ops = &clk_rcg_ops,
13261326
},
13271327
}
@@ -1371,7 +1371,7 @@ static struct clk_rcg sdc3_src = {
13711371
.hw.init = &(struct clk_init_data){
13721372
.name = "sdc3_src",
13731373
.parent_data = gcc_pxo_pll8,
1374-
.num_parents = 2,
1374+
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
13751375
.ops = &clk_rcg_ops,
13761376
},
13771377
}
@@ -1456,7 +1456,7 @@ static struct clk_rcg tsif_ref_src = {
14561456
.hw.init = &(struct clk_init_data){
14571457
.name = "tsif_ref_src",
14581458
.parent_data = gcc_pxo_pll8,
1459-
.num_parents = 2,
1459+
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
14601460
.ops = &clk_rcg_ops,
14611461
},
14621462
}
@@ -1620,7 +1620,7 @@ static struct clk_rcg pcie_ref_src = {
16201620
.hw.init = &(struct clk_init_data){
16211621
.name = "pcie_ref_src",
16221622
.parent_data = gcc_pxo_pll3,
1623-
.num_parents = 2,
1623+
.num_parents = ARRAY_SIZE(gcc_pxo_pll3),
16241624
.ops = &clk_rcg_ops,
16251625
.flags = CLK_SET_RATE_GATE,
16261626
},
@@ -1714,7 +1714,7 @@ static struct clk_rcg pcie1_ref_src = {
17141714
.hw.init = &(struct clk_init_data){
17151715
.name = "pcie1_ref_src",
17161716
.parent_data = gcc_pxo_pll3,
1717-
.num_parents = 2,
1717+
.num_parents = ARRAY_SIZE(gcc_pxo_pll3),
17181718
.ops = &clk_rcg_ops,
17191719
.flags = CLK_SET_RATE_GATE,
17201720
},
@@ -1808,7 +1808,7 @@ static struct clk_rcg pcie2_ref_src = {
18081808
.hw.init = &(struct clk_init_data){
18091809
.name = "pcie2_ref_src",
18101810
.parent_data = gcc_pxo_pll3,
1811-
.num_parents = 2,
1811+
.num_parents = ARRAY_SIZE(gcc_pxo_pll3),
18121812
.ops = &clk_rcg_ops,
18131813
.flags = CLK_SET_RATE_GATE,
18141814
},
@@ -1907,7 +1907,7 @@ static struct clk_rcg sata_ref_src = {
19071907
.hw.init = &(struct clk_init_data){
19081908
.name = "sata_ref_src",
19091909
.parent_data = gcc_pxo_pll3,
1910-
.num_parents = 2,
1910+
.num_parents = ARRAY_SIZE(gcc_pxo_pll3),
19111911
.ops = &clk_rcg_ops,
19121912
.flags = CLK_SET_RATE_GATE,
19131913
},
@@ -2048,7 +2048,7 @@ static struct clk_rcg usb30_master_clk_src = {
20482048
.hw.init = &(struct clk_init_data){
20492049
.name = "usb30_master_ref_src",
20502050
.parent_data = gcc_pxo_pll8_pll0,
2051-
.num_parents = 3,
2051+
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
20522052
.ops = &clk_rcg_ops,
20532053
.flags = CLK_SET_RATE_GATE,
20542054
},
@@ -2122,7 +2122,7 @@ static struct clk_rcg usb30_utmi_clk = {
21222122
.hw.init = &(struct clk_init_data){
21232123
.name = "usb30_utmi_clk",
21242124
.parent_data = gcc_pxo_pll8_pll0,
2125-
.num_parents = 3,
2125+
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
21262126
.ops = &clk_rcg_ops,
21272127
.flags = CLK_SET_RATE_GATE,
21282128
},
@@ -2196,7 +2196,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = {
21962196
.hw.init = &(struct clk_init_data){
21972197
.name = "usb_hs1_xcvr_src",
21982198
.parent_data = gcc_pxo_pll8_pll0,
2199-
.num_parents = 3,
2199+
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
22002200
.ops = &clk_rcg_ops,
22012201
.flags = CLK_SET_RATE_GATE,
22022202
},
@@ -2262,7 +2262,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = {
22622262
.hw.init = &(struct clk_init_data){
22632263
.name = "usb_fs1_xcvr_src",
22642264
.parent_data = gcc_pxo_pll8_pll0,
2265-
.num_parents = 3,
2265+
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
22662266
.ops = &clk_rcg_ops,
22672267
.flags = CLK_SET_RATE_GATE,
22682268
},
@@ -2398,7 +2398,7 @@ static struct clk_dyn_rcg gmac_core1_src = {
23982398
.hw.init = &(struct clk_init_data){
23992399
.name = "gmac_core1_src",
24002400
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
2401-
.num_parents = 5,
2401+
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
24022402
.ops = &clk_dyn_rcg_ops,
24032403
},
24042404
},
@@ -2470,7 +2470,7 @@ static struct clk_dyn_rcg gmac_core2_src = {
24702470
.hw.init = &(struct clk_init_data){
24712471
.name = "gmac_core2_src",
24722472
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
2473-
.num_parents = 5,
2473+
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
24742474
.ops = &clk_dyn_rcg_ops,
24752475
},
24762476
},
@@ -2542,7 +2542,7 @@ static struct clk_dyn_rcg gmac_core3_src = {
25422542
.hw.init = &(struct clk_init_data){
25432543
.name = "gmac_core3_src",
25442544
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
2545-
.num_parents = 5,
2545+
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
25462546
.ops = &clk_dyn_rcg_ops,
25472547
},
25482548
},
@@ -2614,7 +2614,7 @@ static struct clk_dyn_rcg gmac_core4_src = {
26142614
.hw.init = &(struct clk_init_data){
26152615
.name = "gmac_core4_src",
26162616
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
2617-
.num_parents = 5,
2617+
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
26182618
.ops = &clk_dyn_rcg_ops,
26192619
},
26202620
},
@@ -2674,7 +2674,7 @@ static struct clk_dyn_rcg nss_tcm_src = {
26742674
.hw.init = &(struct clk_init_data){
26752675
.name = "nss_tcm_src",
26762676
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
2677-
.num_parents = 5,
2677+
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
26782678
.ops = &clk_dyn_rcg_ops,
26792679
},
26802680
},
@@ -2752,7 +2752,7 @@ static struct clk_dyn_rcg ubi32_core1_src_clk = {
27522752
.hw.init = &(struct clk_init_data){
27532753
.name = "ubi32_core1_src_clk",
27542754
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
2755-
.num_parents = 5,
2755+
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
27562756
.ops = &clk_dyn_rcg_ops,
27572757
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
27582758
},
@@ -2805,7 +2805,7 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = {
28052805
.hw.init = &(struct clk_init_data){
28062806
.name = "ubi32_core2_src_clk",
28072807
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
2808-
.num_parents = 5,
2808+
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
28092809
.ops = &clk_dyn_rcg_ops,
28102810
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
28112811
},

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