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chenhuacaichenhuacai
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Merge 'bpf-next 2023-10-16' into loongarch-next
LoongArch architecture changes for 6.7 (BPF CPU v4 support) depend on the bpf changes to fix conflictions in selftests and work, so merge them to create a base.
2 parents ffc2532 + 99c9991 commit a6bdc08

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‎Documentation/admin-guide/sysctl/net.rst‎

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@@ -71,6 +71,7 @@ two flavors of JITs, the newer eBPF JIT currently supported on:
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- s390x
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- riscv64
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- riscv32
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- loongarch64
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And the older cBPF JIT supported on the following archs:
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‎Documentation/bpf/libbpf/program_types.rst‎

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@@ -56,6 +56,16 @@ described in more detail in the footnotes.
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| | ``BPF_CGROUP_UDP6_RECVMSG`` | ``cgroup/recvmsg6`` | |
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+ +----------------------------------------+----------------------------------+-----------+
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| | ``BPF_CGROUP_UDP6_SENDMSG`` | ``cgroup/sendmsg6`` | |
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| +----------------------------------------+----------------------------------+-----------+
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| | ``BPF_CGROUP_UNIX_CONNECT`` | ``cgroup/connect_unix`` | |
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| +----------------------------------------+----------------------------------+-----------+
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| | ``BPF_CGROUP_UNIX_SENDMSG`` | ``cgroup/sendmsg_unix`` | |
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| +----------------------------------------+----------------------------------+-----------+
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| | ``BPF_CGROUP_UNIX_RECVMSG`` | ``cgroup/recvmsg_unix`` | |
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| +----------------------------------------+----------------------------------+-----------+
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| | ``BPF_CGROUP_UNIX_GETPEERNAME`` | ``cgroup/getpeername_unix`` | |
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| +----------------------------------------+----------------------------------+-----------+
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| | ``BPF_CGROUP_UNIX_GETSOCKNAME`` | ``cgroup/getsockname_unix`` | |
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+-------------------------------------------+----------------------------------------+----------------------------------+-----------+
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| ``BPF_PROG_TYPE_CGROUP_SOCK`` | ``BPF_CGROUP_INET4_POST_BIND`` | ``cgroup/post_bind4`` | |
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+ +----------------------------------------+----------------------------------+-----------+

‎Documentation/bpf/prog_flow_dissector.rst‎

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@@ -113,7 +113,7 @@ Flags
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used by ``eth_get_headlen`` to estimate length of all headers for GRO.
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* ``BPF_FLOW_DISSECTOR_F_STOP_AT_FLOW_LABEL`` - tells BPF flow dissector to
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stop parsing as soon as it reaches IPv6 flow label; used by
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``___skb_get_hash`` and ``__skb_get_hash_symmetric`` to get flow hash.
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``___skb_get_hash`` to get flow hash.
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* ``BPF_FLOW_DISSECTOR_F_STOP_AT_ENCAP`` - tells BPF flow dissector to stop
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parsing as soon as it reaches encapsulated headers; used by routing
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infrastructure.

‎Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml‎

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@@ -22,6 +22,7 @@ properties:
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- mediatek,mt7622-wed
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- mediatek,mt7981-wed
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- mediatek,mt7986-wed
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- mediatek,mt7988-wed
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- const: syscon
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reg:

‎Documentation/devicetree/bindings/mfd/syscon.yaml‎

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@@ -49,6 +49,8 @@ properties:
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- hisilicon,peri-subctrl
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- hpe,gxp-sysreg
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- intel,lgm-syscon
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- loongson,ls1b-syscon
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- loongson,ls1c-syscon
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- marvell,armada-3700-usb2-host-misc
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- mediatek,mt8135-pctl-a-syscfg
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- mediatek,mt8135-pctl-b-syscfg

‎Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml‎

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Set if the output SYNCLKO clock should be disabled. Do not mix with
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microchip,synclko-125.
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microchip,io-drive-strength-microamp:
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description:
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IO Pad Drive Strength
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enum: [8000, 16000]
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default: 16000
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microchip,hi-drive-strength-microamp:
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description:
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High Speed Drive Strength. Controls drive strength of GMII / RGMII /
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MII / RMII (except TX_CLK/REFCLKI, COL and CRS) and CLKO_25_125 lines.
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enum: [2000, 4000, 8000, 12000, 16000, 20000, 24000, 28000]
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default: 24000
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microchip,lo-drive-strength-microamp:
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description:
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Low Speed Drive Strength. Controls drive strength of TX_CLK / REFCLKI,
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COL, CRS, LEDs, PME_N, NTRP_N, SDO and SDI/SDA/MDIO lines.
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enum: [2000, 4000, 8000, 12000, 16000, 20000, 24000, 28000]
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default: 8000
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interrupts:
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maxItems: 1
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‎Documentation/devicetree/bindings/net/loongson,ls1b-gmac.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/loongson,ls1b-gmac.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Loongson-1B Gigabit Ethernet MAC Controller
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maintainers:
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- Keguang Zhang <keguang.zhang@gmail.com>
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description: |
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Loongson-1B Gigabit Ethernet MAC Controller is based on
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Synopsys DesignWare MAC (version 3.50a).
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Main features
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- Dual 10/100/1000Mbps GMAC controllers
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- Full-duplex operation (IEEE 802.3x flow control automatic transmission)
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- Half-duplex operation (CSMA/CD Protocol and back-pressure support)
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- RX Checksum Offload
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- TX Checksum insertion
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- MII interface
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- RGMII interface
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select:
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properties:
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compatible:
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contains:
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enum:
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- loongson,ls1b-gmac
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required:
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- compatible
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properties:
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compatible:
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items:
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- enum:
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- loongson,ls1b-gmac
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- const: snps,dwmac-3.50a
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: stmmaceth
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interrupts:
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maxItems: 1
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interrupt-names:
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items:
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- const: macirq
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loongson,ls1-syscon:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to the syscon containing some extra configurations
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including PHY interface mode.
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phy-mode:
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enum:
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- mii
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- rgmii-id
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- interrupts
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- interrupt-names
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- loongson,ls1-syscon
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allOf:
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- $ref: snps,dwmac.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/loongson,ls1x-clk.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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gmac0: ethernet@1fe10000 {
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compatible = "loongson,ls1b-gmac", "snps,dwmac-3.50a";
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reg = <0x1fe10000 0x10000>;
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clocks = <&clkc LS1X_CLKID_AHB>;
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clock-names = "stmmaceth";
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interrupt-parent = <&intc1>;
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interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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loongson,ls1-syscon = <&syscon>;
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phy-handle = <&phy0>;
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phy-mode = "mii";
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snps,pbl = <1>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy0: ethernet-phy@0 {
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reg = <0x0>;
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};
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};
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};

‎Documentation/devicetree/bindings/net/loongson,ls1c-emac.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/loongson,ls1c-emac.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Loongson-1C Ethernet MAC Controller
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maintainers:
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- Keguang Zhang <keguang.zhang@gmail.com>
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description: |
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Loongson-1C Ethernet MAC Controller is based on
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Synopsys DesignWare MAC (version 3.50a).
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Main features
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- 10/100Mbps
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- Full-duplex operation (IEEE 802.3x flow control automatic transmission)
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- Half-duplex operation (CSMA/CD Protocol and back-pressure support)
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- IEEE 802.1Q VLAN tag detection for reception frames
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- MII interface
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- RMII interface
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select:
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properties:
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compatible:
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contains:
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enum:
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- loongson,ls1c-emac
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required:
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- compatible
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properties:
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compatible:
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items:
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- enum:
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- loongson,ls1c-emac
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- const: snps,dwmac-3.50a
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: stmmaceth
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interrupts:
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maxItems: 1
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interrupt-names:
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items:
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- const: macirq
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loongson,ls1-syscon:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to the syscon containing some extra configurations
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including PHY interface mode.
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phy-mode:
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enum:
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- mii
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- rmii
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- interrupts
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- interrupt-names
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- loongson,ls1-syscon
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allOf:
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- $ref: snps,dwmac.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/loongson,ls1x-clk.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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emac: ethernet@1fe10000 {
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compatible = "loongson,ls1c-emac", "snps,dwmac-3.50a";
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reg = <0x1fe10000 0x10000>;
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clocks = <&clkc LS1X_CLKID_AHB>;
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clock-names = "stmmaceth";
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interrupt-parent = <&intc1>;
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interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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loongson,ls1-syscon = <&syscon>;
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phy-handle = <&phy0>;
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phy-mode = "mii";
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snps,pbl = <1>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy0: ethernet-phy@13 {
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reg = <0x13>;
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};
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};
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};

‎Documentation/devicetree/bindings/net/snps,dwmac.yaml‎

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When a PFC frame is received with priorities matching the bitmask,
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the queue is blocked from transmitting for the pause time specified
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in the PFC frame.
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snps,coe-unsupported:
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type: boolean
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description: TX checksum offload is unsupported by the TX queue.
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allOf:
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- if:
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required:

‎Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml‎

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properties:
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compatible:
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enum:
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- ti,am642-icssg-prueth # for AM64x SoC family
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- ti,am654-icssg-prueth # for AM65x SoC family
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sram:
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phandle to system controller node and register offset
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to ICSSG control register for RGMII transmit delay
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ti,half-duplex-capable:
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type: boolean
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description:
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Indicates that the PHY output pin COL is routed to ICSSG GPIO pin
114+
(PRGx_PRU0/1_GPIO10) as input so that the ICSSG MII port is
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capable of half duplex operations.
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required:
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- reg
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anyOf:

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