6969#define ACR_SSTROBE_MASK BIT(31)
7070#define ASIZE_16BIT 1
7171
72- #define CONFIG_MASK (TA(TA_MAX) | \
73- RHOLD(RHOLD_MAX) | \
74- RSTROBE(RSTROBE_MAX) | \
75- RSETUP(RSETUP_MAX) | \
76- WHOLD(WHOLD_MAX) | \
77- WSTROBE(WSTROBE_MAX) | \
78- WSETUP(WSETUP_MAX) | \
79- EW(EW_MAX) | SSTROBE(SSTROBE_MAX) | \
80- ASIZE_MAX)
72+ #define TIMINGS_MASK (TA(TA_MAX) | \
73+ RHOLD(RHOLD_MAX) | \
74+ RSTROBE(RSTROBE_MAX) | \
75+ RSETUP(RSETUP_MAX) | \
76+ WHOLD(WHOLD_MAX) | \
77+ WSTROBE(WSTROBE_MAX) | \
78+ WSETUP(WSETUP_MAX))
79+
80+ #define CONFIG_MASK (EW(EW_MAX) | SSTROBE(SSTROBE_MAX) | ASIZE_MAX)
8181
8282/**
8383 * struct aemif_cs_timings: structure to hold CS timings
@@ -165,6 +165,44 @@ static int aemif_check_cs_timings(struct aemif_cs_timings *timings)
165165 return 0 ;
166166}
167167
168+ /**
169+ * aemif_set_cs_timings() - Set the timing configuration of a given chip select.
170+ * @aemif: aemif device to configure
171+ * @cs: index of the chip select to configure
172+ * @timings: timings configuration to set
173+ *
174+ * @return: 0 on success, else negative errno.
175+ */
176+ static int aemif_set_cs_timings (struct aemif_device * aemif , u8 cs , struct aemif_cs_timings * timings )
177+ {
178+ unsigned int offset ;
179+ u32 val , set ;
180+ int ret ;
181+
182+ if (!timings || !aemif )
183+ return - EINVAL ;
184+
185+ if (cs > aemif -> num_cs )
186+ return - EINVAL ;
187+
188+ ret = aemif_check_cs_timings (timings );
189+ if (ret )
190+ return ret ;
191+
192+ set = TA (timings -> ta ) | RHOLD (timings -> rhold ) | RSTROBE (timings -> rstrobe ) |
193+ RSETUP (timings -> rsetup ) | WHOLD (timings -> whold ) |
194+ WSTROBE (timings -> wstrobe ) | WSETUP (timings -> wsetup );
195+
196+ offset = A1CR_OFFSET + cs * 4 ;
197+
198+ val = readl (aemif -> base + offset );
199+ val &= ~TIMINGS_MASK ;
200+ val |= set ;
201+ writel (val , aemif -> base + offset );
202+
203+ return 0 ;
204+ }
205+
168206/**
169207 * aemif_calc_rate - calculate timing data.
170208 * @pdev: platform device to calculate for
@@ -213,12 +251,7 @@ static int aemif_config_abus(struct platform_device *pdev, int csnum)
213251
214252 offset = A1CR_OFFSET + (data -> cs - aemif -> cs_offset ) * 4 ;
215253
216- set = TA (data -> timings .ta ) |
217- RHOLD (data -> timings .rhold ) | RSTROBE (data -> timings .rstrobe ) |
218- RSETUP (data -> timings .rsetup ) | WHOLD (data -> timings .whold ) |
219- WSTROBE (data -> timings .wstrobe ) | WSETUP (data -> timings .wsetup );
220-
221- set |= (data -> asize & ACR_ASIZE_MASK );
254+ set = (data -> asize & ACR_ASIZE_MASK );
222255 if (data -> enable_ew )
223256 set |= ACR_EW_MASK ;
224257 if (data -> enable_ss )
@@ -229,7 +262,7 @@ static int aemif_config_abus(struct platform_device *pdev, int csnum)
229262 val |= set ;
230263 writel (val , aemif -> base + offset );
231264
232- return 0 ;
265+ return aemif_set_cs_timings ( aemif , data -> cs - aemif -> cs_offset , & data -> timings ) ;
233266}
234267
235268/**
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