@@ -60,11 +60,11 @@ static inline bool ap_instructions_available(void)
6060 unsigned long reg1 = 0 ;
6161
6262 asm volatile (
63- " lgr 0,%[reg0]\n" /* qid into gr0 */
64- " lghi 1,0\n" /* 0 into gr1 */
65- " lghi 2,0\n" /* 0 into gr2 */
63+ " lgr 0,%[reg0]\n" /* qid into gr0 */
64+ " lghi 1,0\n" /* 0 into gr1 */
65+ " lghi 2,0\n" /* 0 into gr2 */
6666 " .insn rre,0xb2af0000,0,0\n" /* PQAP(TAPQ) */
67- "0: la %[reg1],1\n" /* 1 into reg1 */
67+ "0: la %[reg1],1\n" /* 1 into reg1 */
6868 "1:\n"
6969 EX_TABLE (0b , 1b )
7070 : [reg1 ] "+ & d " (reg1)
@@ -86,11 +86,11 @@ static inline struct ap_queue_status ap_tapq(ap_qid_t qid, unsigned long *info)
8686 unsigned long reg2 ;
8787
8888 asm volatile (
89- " lgr 0,%[qid]\n" /* qid into gr0 */
90- " lghi 2,0\n" /* 0 into gr2 */
89+ " lgr 0,%[qid]\n" /* qid into gr0 */
90+ " lghi 2,0\n" /* 0 into gr2 */
9191 " .insn rre,0xb2af0000,0,0\n" /* PQAP(TAPQ) */
92- " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
93- " lgr %[reg2],2\n" /* gr2 into reg2 */
92+ " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
93+ " lgr %[reg2],2\n" /* gr2 into reg2 */
9494 : [reg1 ] "=&d" (reg1 ), [reg2 ] "=&d" (reg2 )
9595 : [qid ] "d" (qid )
9696 : "cc" , "0" , "1" , "2" );
@@ -128,9 +128,9 @@ static inline struct ap_queue_status ap_rapq(ap_qid_t qid)
128128 struct ap_queue_status reg1 ;
129129
130130 asm volatile (
131- " lgr 0,%[reg0]\n" /* qid arg into gr0 */
131+ " lgr 0,%[reg0]\n" /* qid arg into gr0 */
132132 " .insn rre,0xb2af0000,0,0\n" /* PQAP(RAPQ) */
133- " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
133+ " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
134134 : [reg1 ] "=&d" (reg1 )
135135 : [reg0 ] "d" (reg0 )
136136 : "cc" , "0" , "1" );
@@ -149,9 +149,9 @@ static inline struct ap_queue_status ap_zapq(ap_qid_t qid)
149149 struct ap_queue_status reg1 ;
150150
151151 asm volatile (
152- " lgr 0,%[reg0]\n" /* qid arg into gr0 */
152+ " lgr 0,%[reg0]\n" /* qid arg into gr0 */
153153 " .insn rre,0xb2af0000,0,0\n" /* PQAP(ZAPQ) */
154- " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
154+ " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
155155 : [reg1 ] "=&d" (reg1 )
156156 : [reg0 ] "d" (reg0 )
157157 : "cc" , "0" , "1" );
@@ -190,10 +190,10 @@ static inline int ap_qci(struct ap_config_info *config)
190190 struct ap_config_info * reg2 = config ;
191191
192192 asm volatile (
193- " lgr 0,%[reg0]\n" /* QCI fc into gr0 */
194- " lgr 2,%[reg2]\n" /* ptr to config into gr2 */
193+ " lgr 0,%[reg0]\n" /* QCI fc into gr0 */
194+ " lgr 2,%[reg2]\n" /* ptr to config into gr2 */
195195 " .insn rre,0xb2af0000,0,0\n" /* PQAP(QCI) */
196- "0: la %[reg1],0\n" /* good case, QCI fc available */
196+ "0: la %[reg1],0\n" /* good case, QCI fc available */
197197 "1:\n"
198198 EX_TABLE (0b , 1b )
199199 : [reg1 ] "+ & d " (reg1)
@@ -246,11 +246,11 @@ static inline struct ap_queue_status ap_aqic(ap_qid_t qid,
246246 reg1 .qirqctrl = qirqctrl ;
247247
248248 asm volatile (
249- " lgr 0,%[reg0]\n" /* qid param into gr0 */
250- " lgr 1,%[reg1]\n" /* irq ctrl into gr1 */
251- " lgr 2,%[reg2]\n" /* ni addr into gr2 */
249+ " lgr 0,%[reg0]\n" /* qid param into gr0 */
250+ " lgr 1,%[reg1]\n" /* irq ctrl into gr1 */
251+ " lgr 2,%[reg2]\n" /* ni addr into gr2 */
252252 " .insn rre,0xb2af0000,0,0\n" /* PQAP(AQIC) */
253- " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
253+ " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
254254 : [reg1 ] "+&d" (reg1 )
255255 : [reg0 ] "d" (reg0 ), [reg2 ] "d" (reg2 )
256256 : "cc" , "0" , "1" , "2" );
@@ -297,11 +297,11 @@ static inline struct ap_queue_status ap_qact(ap_qid_t qid, int ifbit,
297297 reg1 .value = apinfo -> val ;
298298
299299 asm volatile (
300- " lgr 0,%[reg0]\n" /* qid param into gr0 */
301- " lgr 1,%[reg1]\n" /* qact in info into gr1 */
300+ " lgr 0,%[reg0]\n" /* qid param into gr0 */
301+ " lgr 1,%[reg1]\n" /* qact in info into gr1 */
302302 " .insn rre,0xb2af0000,0,0\n" /* PQAP(QACT) */
303- " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
304- " lgr %[reg2],2\n" /* qact out info into reg2 */
303+ " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
304+ " lgr %[reg2],2\n" /* qact out info into reg2 */
305305 : [reg1 ] "+&d" (reg1 ), [reg2 ] "=&d" (reg2 )
306306 : [reg0 ] "d" (reg0 )
307307 : "cc" , "0" , "1" , "2" );
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