Skip to content

Commit a8c371f

Browse files
arndbarndb
committed
Merge tag 'v5.14-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/drivers
pm-domains: - correct mask define if used for update on TOPAXI bus - mt8173: enable regulator befor turning on MFG_ASYNC mmsys: - add a mask property to the routing information - add support for MT8365 - add UFOE routing for MT8173 * tag 'v5.14-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: soc: mediatek: mmsys: Fix missing UFOE component in mt8173 table routing soc: mediatek: mmsys: add MT8365 support soc: mmsys: mediatek: add mask to mmsys routes soc: mediatek: pm-domains: Add domain_supply cap for mfg_async PD soc: mediatek: pm-domains: Use correct mask for bus_prot_clr Link: https://lore.kernel.org/r/49fc7bef-20db-b98c-9437-dd9e4d00e870@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 parents a41461b + 2542373 commit a8c371f

6 files changed

Lines changed: 189 additions & 50 deletions

File tree

‎drivers/soc/mediatek/mt8173-pm-domains.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -71,6 +71,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
7171
.ctl_offs = SPM_MFG_ASYNC_PWR_CON,
7272
.sram_pdn_bits = GENMASK(11, 8),
7373
.sram_pdn_ack_bits = 0,
74+
.caps = MTK_SCPD_DOMAIN_SUPPLY,
7475
},
7576
[MT8173_POWER_DOMAIN_MFG_2D] = {
7677
.name = "mfg_2d",

‎drivers/soc/mediatek/mt8183-mmsys.h‎

Lines changed: 14 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -28,25 +28,32 @@
2828
static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
2929
{
3030
DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
31-
MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L
31+
MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L,
32+
MT8183_OVL0_MOUT_EN_OVL0_2L
3233
}, {
3334
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
34-
MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0
35+
MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0,
36+
MT8183_OVL0_2L_MOUT_EN_DISP_PATH0
3537
}, {
3638
DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_RDMA1,
37-
MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1
39+
MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1,
40+
MT8183_OVL1_2L_MOUT_EN_RDMA1
3841
}, {
3942
DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
40-
MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0
43+
MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0,
44+
MT8183_DITHER0_MOUT_IN_DSI0
4145
}, {
4246
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
43-
MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L
47+
MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L,
48+
MT8183_DISP_PATH0_SEL_IN_OVL0_2L
4449
}, {
4550
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
46-
MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1
51+
MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1,
52+
MT8183_DPI0_SEL_IN_RDMA1
4753
}, {
4854
DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
49-
MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0
55+
MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0,
56+
MT8183_RDMA0_SOUT_COLOR0
5057
}
5158
};
5259

‎drivers/soc/mediatek/mt8365-mmsys.h‎

Lines changed: 60 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,60 @@
1+
/* SPDX-License-Identifier: GPL-2.0-only */
2+
3+
#ifndef __SOC_MEDIATEK_MT8365_MMSYS_H
4+
#define __SOC_MEDIATEK_MT8365_MMSYS_H
5+
6+
#define MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0xf3c
7+
#define MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL 0xf4c
8+
#define MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN 0xf50
9+
#define MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN 0xf54
10+
#define MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN 0xf60
11+
#define MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0xf64
12+
#define MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN 0xf68
13+
14+
#define MT8365_RDMA0_SOUT_COLOR0 0x1
15+
#define MT8365_DITHER_MOUT_EN_DSI0 0x1
16+
#define MT8365_DSI0_SEL_IN_DITHER 0x1
17+
#define MT8365_RDMA0_SEL_IN_OVL0 0x0
18+
#define MT8365_RDMA0_RSZ0_SEL_IN_RDMA0 0x0
19+
#define MT8365_DISP_COLOR_SEL_IN_COLOR0 0x0
20+
#define MT8365_OVL0_MOUT_PATH0_SEL BIT(0)
21+
22+
static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {
23+
{
24+
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
25+
MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
26+
MT8365_OVL0_MOUT_PATH0_SEL, MT8365_OVL0_MOUT_PATH0_SEL
27+
},
28+
{
29+
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
30+
MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN,
31+
MT8365_RDMA0_SEL_IN_OVL0, MT8365_RDMA0_SEL_IN_OVL0
32+
},
33+
{
34+
DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
35+
MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL,
36+
MT8365_RDMA0_SOUT_COLOR0, MT8365_RDMA0_SOUT_COLOR0
37+
},
38+
{
39+
DDP_COMPONENT_COLOR0, DDP_COMPONENT_CCORR,
40+
MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,
41+
MT8365_DISP_COLOR_SEL_IN_COLOR0,MT8365_DISP_COLOR_SEL_IN_COLOR0
42+
},
43+
{
44+
DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
45+
MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
46+
MT8365_DITHER_MOUT_EN_DSI0, MT8365_DITHER_MOUT_EN_DSI0
47+
},
48+
{
49+
DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
50+
MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
51+
MT8365_DSI0_SEL_IN_DITHER, MT8365_DSI0_SEL_IN_DITHER
52+
},
53+
{
54+
DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
55+
MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN,
56+
MT8365_RDMA0_RSZ0_SEL_IN_RDMA0, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0
57+
},
58+
};
59+
60+
#endif /* __SOC_MEDIATEK_MT8365_MMSYS_H */

‎drivers/soc/mediatek/mtk-mmsys.c‎

Lines changed: 16 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@
1313
#include "mtk-mmsys.h"
1414
#include "mt8167-mmsys.h"
1515
#include "mt8183-mmsys.h"
16+
#include "mt8365-mmsys.h"
1617

1718
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
1819
.clk_driver = "clk-mt2701-mm",
@@ -52,6 +53,12 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
5253
.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
5354
};
5455

56+
static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
57+
.clk_driver = "clk-mt8365-mm",
58+
.routes = mt8365_mmsys_routing_table,
59+
.num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
60+
};
61+
5562
struct mtk_mmsys {
5663
void __iomem *regs;
5764
const struct mtk_mmsys_driver_data *data;
@@ -68,7 +75,9 @@ void mtk_mmsys_ddp_connect(struct device *dev,
6875

6976
for (i = 0; i < mmsys->data->num_routes; i++)
7077
if (cur == routes[i].from_comp && next == routes[i].to_comp) {
71-
reg = readl_relaxed(mmsys->regs + routes[i].addr) | routes[i].val;
78+
reg = readl_relaxed(mmsys->regs + routes[i].addr);
79+
reg &= ~routes[i].mask;
80+
reg |= routes[i].val;
7281
writel_relaxed(reg, mmsys->regs + routes[i].addr);
7382
}
7483
}
@@ -85,7 +94,8 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
8594

8695
for (i = 0; i < mmsys->data->num_routes; i++)
8796
if (cur == routes[i].from_comp && next == routes[i].to_comp) {
88-
reg = readl_relaxed(mmsys->regs + routes[i].addr) & ~routes[i].val;
97+
reg = readl_relaxed(mmsys->regs + routes[i].addr);
98+
reg &= ~routes[i].mask;
8999
writel_relaxed(reg, mmsys->regs + routes[i].addr);
90100
}
91101
}
@@ -157,6 +167,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
157167
.compatible = "mediatek,mt8183-mmsys",
158168
.data = &mt8183_mmsys_driver_data,
159169
},
170+
{
171+
.compatible = "mediatek,mt8365-mmsys",
172+
.data = &mt8365_mmsys_driver_data,
173+
},
160174
{ }
161175
};
162176

0 commit comments

Comments
 (0)