Skip to content

Commit a9d4aff

Browse files
Russell King (Oracle)kuba-moo
Russell King (Oracle)
authored and
kuba-moo
committed
net: stmmac: rk: replace empty set_to_rmii() with supports_rmii
Rather than providing a now-empty set_to_rmii() method to indicate that RMII is supported, switch to setting ops->supports_rmii instead. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Heiko Stuebner <heiko@sntech.de> #px30,rk3328,rk3568,rk3588 Link: https://patch.msgid.link/E1vnYxq-00000007hor-3yXt@rmk-PC.armlinux.org.uk Signed-off-by: Jakub Kicinski <kuba@kernel.org>
1 parent d323769 commit a9d4aff

1 file changed

Lines changed: 24 additions & 62 deletions

File tree

‎drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c‎

Lines changed: 24 additions & 62 deletions
Original file line numberDiff line numberDiff line change
@@ -268,19 +268,16 @@ static void rk_gmac_integrated_fephy_powerdown(struct rk_priv_data *priv,
268268

269269
#define PX30_GRF_GMAC_CON1 0x0904
270270

271-
static void px30_set_to_rmii(struct rk_priv_data *bsp_priv)
272-
{
273-
}
274-
275271
static const struct rk_gmac_ops px30_ops = {
276-
.set_to_rmii = px30_set_to_rmii,
277272
.set_speed = rk_set_clk_mac_speed,
278273

279274
.gmac_grf_reg = PX30_GRF_GMAC_CON1,
280275
.gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
281276

282277
.clock_grf_reg = PX30_GRF_GMAC_CON1,
283278
.clock.mac_speed_mask = BIT_U16(2),
279+
280+
.supports_rmii = true,
284281
};
285282

286283
#define RK3128_GRF_MAC_CON0 0x0168
@@ -307,13 +304,8 @@ static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv,
307304
RK3128_GMAC_CLK_TX_DL_CFG(tx_delay));
308305
}
309306

310-
static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
311-
{
312-
}
313-
314307
static const struct rk_gmac_ops rk3128_ops = {
315308
.set_to_rgmii = rk3128_set_to_rgmii,
316-
.set_to_rmii = rk3128_set_to_rmii,
317309

318310
.gmac_grf_reg = RK3128_GRF_MAC_CON1,
319311
.gmac_phy_intf_sel_mask = GENMASK_U16(8, 6),
@@ -323,6 +315,8 @@ static const struct rk_gmac_ops rk3128_ops = {
323315
.clock.gmii_clk_sel_mask = GENMASK_U16(13, 12),
324316
.clock.rmii_clk_sel_mask = BIT_U16(11),
325317
.clock.mac_speed_mask = BIT_U16(10),
318+
319+
.supports_rmii = true,
326320
};
327321

328322
#define RK3228_GRF_MAC_CON0 0x0900
@@ -410,13 +404,8 @@ static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
410404
RK3288_GMAC_CLK_TX_DL_CFG(tx_delay));
411405
}
412406

413-
static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
414-
{
415-
}
416-
417407
static const struct rk_gmac_ops rk3288_ops = {
418408
.set_to_rgmii = rk3288_set_to_rgmii,
419-
.set_to_rmii = rk3288_set_to_rmii,
420409

421410
.gmac_grf_reg = RK3288_GRF_SOC_CON1,
422411
.gmac_phy_intf_sel_mask = GENMASK_U16(8, 6),
@@ -426,6 +415,8 @@ static const struct rk_gmac_ops rk3288_ops = {
426415
.clock.gmii_clk_sel_mask = GENMASK_U16(13, 12),
427416
.clock.rmii_clk_sel_mask = BIT_U16(11),
428417
.clock.mac_speed_mask = BIT_U16(10),
418+
419+
.supports_rmii = true,
429420
};
430421

431422
#define RK3308_GRF_MAC_CON0 0x04a0
@@ -434,18 +425,14 @@ static const struct rk_gmac_ops rk3288_ops = {
434425
#define RK3308_GMAC_FLOW_CTRL GRF_BIT(3)
435426
#define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
436427

437-
static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv)
438-
{
439-
}
440-
441428
static const struct rk_gmac_ops rk3308_ops = {
442-
.set_to_rmii = rk3308_set_to_rmii,
443-
444429
.gmac_grf_reg = RK3308_GRF_MAC_CON0,
445430
.gmac_phy_intf_sel_mask = GENMASK_U16(4, 2),
446431

447432
.clock_grf_reg = RK3308_GRF_MAC_CON0,
448433
.clock.mac_speed_mask = BIT_U16(0),
434+
435+
.supports_rmii = true,
449436
};
450437

451438
#define RK3328_GRF_MAC_CON0 0x0900
@@ -497,10 +484,6 @@ static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
497484
RK3328_GMAC_CLK_TX_DL_CFG(tx_delay));
498485
}
499486

500-
static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
501-
{
502-
}
503-
504487
static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
505488
{
506489
regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
@@ -512,7 +495,6 @@ static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
512495
static const struct rk_gmac_ops rk3328_ops = {
513496
.init = rk3328_init,
514497
.set_to_rgmii = rk3328_set_to_rgmii,
515-
.set_to_rmii = rk3328_set_to_rmii,
516498
.integrated_phy_powerup = rk3328_integrated_phy_powerup,
517499
.integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown,
518500

@@ -522,6 +504,8 @@ static const struct rk_gmac_ops rk3328_ops = {
522504
.clock.rmii_clk_sel_mask = BIT_U16(7),
523505
.clock.mac_speed_mask = BIT_U16(2),
524506

507+
.supports_rmii = true,
508+
525509
.regs_valid = true,
526510
.regs = {
527511
0xff540000, /* gmac2io */
@@ -554,13 +538,8 @@ static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
554538
RK3366_GMAC_CLK_TX_DL_CFG(tx_delay));
555539
}
556540

557-
static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
558-
{
559-
}
560-
561541
static const struct rk_gmac_ops rk3366_ops = {
562542
.set_to_rgmii = rk3366_set_to_rgmii,
563-
.set_to_rmii = rk3366_set_to_rmii,
564543

565544
.gmac_grf_reg = RK3366_GRF_SOC_CON6,
566545
.gmac_phy_intf_sel_mask = GENMASK_U16(11, 9),
@@ -570,6 +549,8 @@ static const struct rk_gmac_ops rk3366_ops = {
570549
.clock.gmii_clk_sel_mask = GENMASK_U16(5, 4),
571550
.clock.rmii_clk_sel_mask = BIT_U16(3),
572551
.clock.mac_speed_mask = BIT_U16(7),
552+
553+
.supports_rmii = true,
573554
};
574555

575556
#define RK3368_GRF_SOC_CON15 0x043c
@@ -596,13 +577,8 @@ static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
596577
RK3368_GMAC_CLK_TX_DL_CFG(tx_delay));
597578
}
598579

599-
static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
600-
{
601-
}
602-
603580
static const struct rk_gmac_ops rk3368_ops = {
604581
.set_to_rgmii = rk3368_set_to_rgmii,
605-
.set_to_rmii = rk3368_set_to_rmii,
606582

607583
.gmac_grf_reg = RK3368_GRF_SOC_CON15,
608584
.gmac_phy_intf_sel_mask = GENMASK_U16(11, 9),
@@ -612,6 +588,8 @@ static const struct rk_gmac_ops rk3368_ops = {
612588
.clock.gmii_clk_sel_mask = GENMASK_U16(5, 4),
613589
.clock.rmii_clk_sel_mask = BIT_U16(3),
614590
.clock.mac_speed_mask = BIT_U16(7),
591+
592+
.supports_rmii = true,
615593
};
616594

617595
#define RK3399_GRF_SOC_CON5 0xc214
@@ -638,13 +616,8 @@ static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,
638616
RK3399_GMAC_CLK_TX_DL_CFG(tx_delay));
639617
}
640618

641-
static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
642-
{
643-
}
644-
645619
static const struct rk_gmac_ops rk3399_ops = {
646620
.set_to_rgmii = rk3399_set_to_rgmii,
647-
.set_to_rmii = rk3399_set_to_rmii,
648621

649622
.gmac_grf_reg = RK3399_GRF_SOC_CON5,
650623
.gmac_phy_intf_sel_mask = GENMASK_U16(11, 9),
@@ -654,6 +627,8 @@ static const struct rk_gmac_ops rk3399_ops = {
654627
.clock.gmii_clk_sel_mask = GENMASK_U16(5, 4),
655628
.clock.rmii_clk_sel_mask = BIT_U16(3),
656629
.clock.mac_speed_mask = BIT_U16(7),
630+
631+
.supports_rmii = true,
657632
};
658633

659634
#define RK3506_GRF_SOC_CON8 0x0020
@@ -884,18 +859,15 @@ static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv,
884859
RK3568_GMAC_TXCLK_DLY_ENABLE);
885860
}
886861

887-
static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv)
888-
{
889-
}
890-
891862
static const struct rk_gmac_ops rk3568_ops = {
892863
.init = rk3568_init,
893864
.set_to_rgmii = rk3568_set_to_rgmii,
894-
.set_to_rmii = rk3568_set_to_rmii,
895865
.set_speed = rk_set_clk_mac_speed,
896866

897867
.gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
898868

869+
.supports_rmii = true,
870+
899871
.regs_valid = true,
900872
.regs = {
901873
0xfe2a0000, /* gmac0 */
@@ -969,10 +941,6 @@ static void rk3576_set_to_rgmii(struct rk_priv_data *bsp_priv,
969941
RK3576_GMAC_CLK_RX_DL_CFG(rx_delay));
970942
}
971943

972-
static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv)
973-
{
974-
}
975-
976944
static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
977945
bool enable)
978946
{
@@ -992,14 +960,15 @@ static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input
992960
static const struct rk_gmac_ops rk3576_ops = {
993961
.init = rk3576_init,
994962
.set_to_rgmii = rk3576_set_to_rgmii,
995-
.set_to_rmii = rk3576_set_to_rmii,
996963
.set_clock_selection = rk3576_set_clock_selection,
997964

998965
.gmac_rmii_mode_mask = BIT_U16(3),
999966

1000967
.clock.gmii_clk_sel_mask = GENMASK_U16(6, 5),
1001968
.clock.rmii_clk_sel_mask = BIT_U16(5),
1002969

970+
.supports_rmii = true,
971+
1003972
.php_grf_required = true,
1004973
.regs_valid = true,
1005974
.regs = {
@@ -1120,19 +1089,15 @@ static const struct rk_gmac_ops rk3588_ops = {
11201089
#define RV1108_GMAC_FLOW_CTRL GRF_BIT(3)
11211090
#define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
11221091

1123-
static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv)
1124-
{
1125-
}
1126-
11271092
static const struct rk_gmac_ops rv1108_ops = {
1128-
.set_to_rmii = rv1108_set_to_rmii,
1129-
11301093
.gmac_grf_reg = RV1108_GRF_GMAC_CON0,
11311094
.gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
11321095

11331096
.clock_grf_reg = RV1108_GRF_GMAC_CON0,
11341097
.clock.rmii_clk_sel_mask = BIT_U16(7),
11351098
.clock.mac_speed_mask = BIT_U16(2),
1099+
1100+
.supports_rmii = true,
11361101
};
11371102

11381103
#define RV1126_GRF_GMAC_CON0 0X0070
@@ -1176,17 +1141,14 @@ static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv,
11761141
RV1126_GMAC_M1_CLK_TX_DL_CFG(tx_delay));
11771142
}
11781143

1179-
static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv)
1180-
{
1181-
}
1182-
11831144
static const struct rk_gmac_ops rv1126_ops = {
11841145
.set_to_rgmii = rv1126_set_to_rgmii,
1185-
.set_to_rmii = rv1126_set_to_rmii,
11861146
.set_speed = rk_set_clk_mac_speed,
11871147

11881148
.gmac_grf_reg = RV1126_GRF_GMAC_CON0,
11891149
.gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
1150+
1151+
.supports_rmii = true,
11901152
};
11911153

11921154
static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)

0 commit comments

Comments
 (0)