drm/amdgpu/nbio4.3: set proper rmmio_remap.reg_offset for SR-IOV

alexdeucher · alexdeucher · commit ab43213e7afd · 2023-09-11T18:19:48.000-04:00
Needed for HDP flush to work correctly.

Reviewed-by: Timmy Tsai &lt;timmtsai@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
@@ -345,6 +345,9 @@ static void nbio_v4_3_init_registers(struct amdgpu_device *adev)
 		data &= ~RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK;
 		WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2, data);
 	}
+	if (amdgpu_sriov_vf(adev))
+		adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
+			regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
 }
 
 static u32 nbio_v4_3_get_rom_offset(struct amdgpu_device *adev)

Original file line number	Diff line number	Diff line change
`@@ -345,6 +345,9 @@ static void nbio_v4_3_init_registers(struct amdgpu_device *adev)`
`345`	`345`	`data &= ~RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK;`
`346`	`346`	`WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2, data);`
`347`	`347`	`}`
	`348`	`+ if (amdgpu_sriov_vf(adev))`
	`349`	`+ adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,`
	`350`	`+ regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;`
`348`	`351`	`}`
`349`	`352`
`350`	`353`	`static u32 nbio_v4_3_get_rom_offset(struct amdgpu_device *adev)`