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PCI: Move pci_clear_and_set_dword() helper to PCI header
The clear and set pattern is commonly used for accessing PCI config, move the helper pci_clear_and_set_dword() from aspm.c into PCI header. In addition, rename to pci_clear_and_set_config_dword() to retain the "config" information and match the other accessors. No functional change intended. Signed-off-by: Shuai Xue <xueshuai@linux.alibaba.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> Link: https://lore.kernel.org/r/20231208025652.87192-4-xueshuai@linux.alibaba.com Signed-off-by: Will Deacon <will@kernel.org>
1 parent ad6534c commit ac16087

3 files changed

Lines changed: 44 additions & 35 deletions

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‎drivers/pci/access.c‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -598,3 +598,15 @@ int pci_write_config_dword(const struct pci_dev *dev, int where,
598598
return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
599599
}
600600
EXPORT_SYMBOL(pci_write_config_dword);
601+
602+
void pci_clear_and_set_config_dword(const struct pci_dev *dev, int pos,
603+
u32 clear, u32 set)
604+
{
605+
u32 val;
606+
607+
pci_read_config_dword(dev, pos, &val);
608+
val &= ~clear;
609+
val |= set;
610+
pci_write_config_dword(dev, pos, val);
611+
}
612+
EXPORT_SYMBOL(pci_clear_and_set_config_dword);

‎drivers/pci/pcie/aspm.c‎

Lines changed: 30 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -426,17 +426,6 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
426426
}
427427
}
428428

429-
static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos,
430-
u32 clear, u32 set)
431-
{
432-
u32 val;
433-
434-
pci_read_config_dword(pdev, pos, &val);
435-
val &= ~clear;
436-
val |= set;
437-
pci_write_config_dword(pdev, pos, val);
438-
}
439-
440429
/* Calculate L1.2 PM substate timing parameters */
441430
static void aspm_calc_l12_info(struct pcie_link_state *link,
442431
u32 parent_l1ss_cap, u32 child_l1ss_cap)
@@ -501,33 +490,39 @@ static void aspm_calc_l12_info(struct pcie_link_state *link,
501490
cl1_2_enables = cctl1 & PCI_L1SS_CTL1_L1_2_MASK;
502491

503492
if (pl1_2_enables || cl1_2_enables) {
504-
pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
505-
PCI_L1SS_CTL1_L1_2_MASK, 0);
506-
pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
507-
PCI_L1SS_CTL1_L1_2_MASK, 0);
493+
pci_clear_and_set_config_dword(child,
494+
child->l1ss + PCI_L1SS_CTL1,
495+
PCI_L1SS_CTL1_L1_2_MASK, 0);
496+
pci_clear_and_set_config_dword(parent,
497+
parent->l1ss + PCI_L1SS_CTL1,
498+
PCI_L1SS_CTL1_L1_2_MASK, 0);
508499
}
509500

510501
/* Program T_POWER_ON times in both ports */
511502
pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, ctl2);
512503
pci_write_config_dword(child, child->l1ss + PCI_L1SS_CTL2, ctl2);
513504

514505
/* Program Common_Mode_Restore_Time in upstream device */
515-
pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
516-
PCI_L1SS_CTL1_CM_RESTORE_TIME, ctl1);
506+
pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
507+
PCI_L1SS_CTL1_CM_RESTORE_TIME, ctl1);
517508

518509
/* Program LTR_L1.2_THRESHOLD time in both ports */
519-
pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
520-
PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
521-
PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1);
522-
pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
523-
PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
524-
PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1);
510+
pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
511+
PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
512+
PCI_L1SS_CTL1_LTR_L12_TH_SCALE,
513+
ctl1);
514+
pci_clear_and_set_config_dword(child, child->l1ss + PCI_L1SS_CTL1,
515+
PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
516+
PCI_L1SS_CTL1_LTR_L12_TH_SCALE,
517+
ctl1);
525518

526519
if (pl1_2_enables || cl1_2_enables) {
527-
pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1, 0,
528-
pl1_2_enables);
529-
pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1, 0,
530-
cl1_2_enables);
520+
pci_clear_and_set_config_dword(parent,
521+
parent->l1ss + PCI_L1SS_CTL1, 0,
522+
pl1_2_enables);
523+
pci_clear_and_set_config_dword(child,
524+
child->l1ss + PCI_L1SS_CTL1, 0,
525+
cl1_2_enables);
531526
}
532527
}
533528

@@ -687,10 +682,10 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
687682
*/
688683

689684
/* Disable all L1 substates */
690-
pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
691-
PCI_L1SS_CTL1_L1SS_MASK, 0);
692-
pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
693-
PCI_L1SS_CTL1_L1SS_MASK, 0);
685+
pci_clear_and_set_config_dword(child, child->l1ss + PCI_L1SS_CTL1,
686+
PCI_L1SS_CTL1_L1SS_MASK, 0);
687+
pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
688+
PCI_L1SS_CTL1_L1SS_MASK, 0);
694689
/*
695690
* If needed, disable L1, and it gets enabled later
696691
* in pcie_config_aspm_link().
@@ -713,10 +708,10 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
713708
val |= PCI_L1SS_CTL1_PCIPM_L1_2;
714709

715710
/* Enable what we need to enable */
716-
pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
717-
PCI_L1SS_CTL1_L1SS_MASK, val);
718-
pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
719-
PCI_L1SS_CTL1_L1SS_MASK, val);
711+
pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
712+
PCI_L1SS_CTL1_L1SS_MASK, val);
713+
pci_clear_and_set_config_dword(child, child->l1ss + PCI_L1SS_CTL1,
714+
PCI_L1SS_CTL1_L1SS_MASK, val);
720715
}
721716

722717
static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)

‎include/linux/pci.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1239,6 +1239,8 @@ int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
12391239
int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
12401240
int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
12411241
int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1242+
void pci_clear_and_set_config_dword(const struct pci_dev *dev, int pos,
1243+
u32 clear, u32 set);
12421244

12431245
int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
12441246
int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);

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