Skip to content

Commit ada1239

Browse files
committed
Merge tag 'mvebu-dt-6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt
mvebu dt for 6.9 (part 1) a38x: improve solidrun armada 388 clearfog GTR device support: Initial device-tree merge for Clearfog GTR devices had issues causing problems with sfp connectors. The fixes are: - Converted armada-38x dt-bindings to yaml and replaced invalid compatibles. - Added pinctrl nodes for all referenced gpios and removed invalid io from first sfp connector. - Added descriptions for secondary sfp connector and updated labels of dsa switch ports. * tag 'mvebu-dt-6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu: arm: dts: marvell: clearfog-gtr-l8: align port numbers with enclosure arm: dts: marvell: clearfog-gtr-l8: add support for second sfp connector arm: dts: marvell: clearfog-gtr: add missing pinctrl for all used gpios arm: dts: marvell: clearfog-gtr: sort pinctrl nodes alphabetically arm: dts: marvell: clearfog-gtr: add board-specific compatible strings arm: dts: marvell: clearfog: add pro variant compatible in legacy dts dt-bindings: marvell: a38x: add solidrun armada 385 clearfog gtr boards dt-bindings: marvell: a38x: add kobol helios-4 board dt-bindings: marvell: a38x: add solidrun armada 388 clearfog boards dt-bindings: marvell: a38x: convert soc compatibles to yaml Link: https://lore.kernel.org/r/87cysehr9k.fsf@BL-laptop Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 parents ba5b25b + 2f9086e commit ada1239

6 files changed

Lines changed: 167 additions & 59 deletions

File tree

Documentation/devicetree/bindings/arm/marvell/armada-38x.txt

Lines changed: 0 additions & 27 deletions
This file was deleted.
Lines changed: 70 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,70 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/arm/marvell/armada-38x.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Marvell Armada 38x Platforms
8+
9+
maintainers:
10+
- Gregory CLEMENT <gregory.clement@bootlin.com>
11+
12+
properties:
13+
$nodename:
14+
const: '/'
15+
compatible:
16+
oneOf:
17+
18+
- description:
19+
Netgear Armada 380 GS110EM Managed Switch.
20+
items:
21+
- const: netgear,gs110emx
22+
- const: marvell,armada380
23+
24+
- description:
25+
Marvell Armada 385 Development Boards.
26+
items:
27+
- enum:
28+
- marvell,a385-db-amc
29+
- marvell,a385-db-ap
30+
- const: marvell,armada385
31+
- const: marvell,armada380
32+
33+
- description:
34+
SolidRun Armada 385 based single-board computers.
35+
items:
36+
- enum:
37+
- solidrun,clearfog-gtr-l8
38+
- solidrun,clearfog-gtr-s4
39+
- const: marvell,armada385
40+
- const: marvell,armada380
41+
42+
- description:
43+
Kobol Armada 388 based Helios-4 NAS.
44+
items:
45+
- const: kobol,helios4
46+
- const: marvell,armada388
47+
- const: marvell,armada385
48+
- const: marvell,armada380
49+
50+
- description:
51+
Marvell Armada 388 Development Boards.
52+
items:
53+
- enum:
54+
- marvell,a388-gp
55+
- const: marvell,armada388
56+
- const: marvell,armada385
57+
- const: marvell,armada380
58+
59+
- description:
60+
SolidRun Armada 388 clearfog family single-board computers.
61+
items:
62+
- enum:
63+
- solidrun,clearfog-base-a1
64+
- solidrun,clearfog-pro-a1
65+
- const: solidrun,clearfog-a1
66+
- const: marvell,armada388
67+
- const: marvell,armada385
68+
- const: marvell,armada380
69+
70+
additionalProperties: true

arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts

Lines changed: 29 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,18 @@
44

55
/ {
66
model = "SolidRun Clearfog GTR L8";
7+
compatible = "solidrun,clearfog-gtr-l8", "marvell,armada385",
8+
"marvell,armada380";
9+
10+
/* CON25 */
11+
sfp1: sfp-1 {
12+
compatible = "sff,sfp";
13+
pinctrl-0 = <&cf_gtr_sfp1_pins>;
14+
pinctrl-names = "default";
15+
i2c-bus = <&i2c0>;
16+
mod-def0-gpio = <&gpio0 24 GPIO_ACTIVE_LOW>;
17+
tx-disable-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
18+
};
719
};
820

921
&mdio {
@@ -20,57 +32,65 @@
2032

2133
ethernet-port@1 {
2234
reg = <1>;
23-
label = "lan8";
35+
label = "lan1";
2436
phy-handle = <&switch0phy0>;
2537
};
2638

2739
ethernet-port@2 {
2840
reg = <2>;
29-
label = "lan7";
41+
label = "lan2";
3042
phy-handle = <&switch0phy1>;
3143
};
3244

3345
ethernet-port@3 {
3446
reg = <3>;
35-
label = "lan6";
47+
label = "lan3";
3648
phy-handle = <&switch0phy2>;
3749
};
3850

3951
ethernet-port@4 {
4052
reg = <4>;
41-
label = "lan5";
53+
label = "lan4";
4254
phy-handle = <&switch0phy3>;
4355
};
4456

4557
ethernet-port@5 {
4658
reg = <5>;
47-
label = "lan4";
59+
label = "lan5";
4860
phy-handle = <&switch0phy4>;
4961
};
5062

5163
ethernet-port@6 {
5264
reg = <6>;
53-
label = "lan3";
65+
label = "lan6";
5466
phy-handle = <&switch0phy5>;
5567
};
5668

5769
ethernet-port@7 {
5870
reg = <7>;
59-
label = "lan2";
71+
label = "lan7";
6072
phy-handle = <&switch0phy6>;
6173
};
6274

6375
ethernet-port@8 {
6476
reg = <8>;
65-
label = "lan1";
77+
label = "lan8";
6678
phy-handle = <&switch0phy7>;
6779
};
6880

81+
ethernet-port@9 {
82+
reg = <9>;
83+
label = "lan-sfp";
84+
phy-mode = "sgmii";
85+
sfp = <&sfp1>;
86+
managed = "in-band-status";
87+
};
88+
6989
ethernet-port@10 {
7090
reg = <10>;
7191
phy-mode = "2500base-x";
72-
7392
ethernet = <&eth1>;
93+
7494
fixed-link {
7595
speed = <2500>;
7696
full-duplex;

arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,8 @@
44

55
/ {
66
model = "SolidRun Clearfog GTR S4";
7+
compatible = "solidrun,clearfog-gtr-s4", "marvell,armada385",
8+
"marvell,armada380";
79
};
810

911
&sfp0 {

arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi

Lines changed: 63 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -141,18 +141,13 @@
141141
};
142142

143143
pinctrl@18000 {
144-
cf_gtr_switch_reset_pins: cf-gtr-switch-reset-pins {
145-
marvell,pins = "mpp18";
146-
marvell,function = "gpio";
147-
};
148-
149-
cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus {
150-
marvell,pins = "mpp22";
144+
cf_gtr_fan_pwm: cf-gtr-fan-pwm {
145+
marvell,pins = "mpp23";
151146
marvell,function = "gpio";
152147
};
153148

154-
cf_gtr_fan_pwm: cf-gtr-fan-pwm {
155-
marvell,pins = "mpp23";
149+
cf_gtr_front_button_pins: cf-gtr-front-button-pins {
150+
marvell,pins = "mpp53";
156151
marvell,function = "gpio";
157152
};
158153

@@ -162,20 +157,53 @@
162157
marvell,function = "i2c1";
163158
};
164159

160+
cf_gtr_isolation_pins: cf-gtr-isolation-pins {
161+
marvell,pins = "mpp47";
162+
marvell,function = "gpio";
163+
};
164+
165+
cf_gtr_led_pins: led-pins {
166+
marvell,pins = "mpp42", "mpp52";
167+
marvell,function = "gpio";
168+
};
169+
170+
cf_gtr_lte_disable_pins: lte-disable-pins {
171+
marvell,pins = "mpp34";
172+
marvell,function = "gpio";
173+
};
174+
175+
cf_gtr_pci_pins: pci-pins {
176+
// pci reset
177+
marvell,pins = "mpp33", "mpp35", "mpp44";
178+
marvell,function = "gpio";
179+
};
180+
181+
cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins {
182+
marvell,pins = "mpp48";
183+
marvell,function = "gpio";
184+
};
185+
186+
cf_gtr_rear_button_pins: cf-gtr-rear-button-pins {
187+
marvell,pins = "mpp36";
188+
marvell,function = "gpio";
189+
};
190+
165191
cf_gtr_sdhci_pins: cf-gtr-sdhci-pins {
166192
marvell,pins = "mpp21", "mpp28",
167193
"mpp37", "mpp38",
168194
"mpp39", "mpp40";
169195
marvell,function = "sd0";
170196
};
171197

172-
cf_gtr_isolation_pins: cf-gtr-isolation-pins {
173-
marvell,pins = "mpp47";
198+
cf_gtr_sfp0_pins: sfp0-pins {
199+
/* sfp modabs, txdisable */
200+
marvell,pins = "mpp25", "mpp46";
174201
marvell,function = "gpio";
175202
};
176203

177-
cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins {
178-
marvell,pins = "mpp48";
204+
cf_gtr_sfp1_pins: sfp1-pins {
205+
/* sfp modabs, txdisable */
206+
marvell,pins = "mpp24", "mpp54";
179207
marvell,function = "gpio";
180208
};
181209

@@ -184,13 +212,18 @@
184212
marvell,function = "spi1";
185213
};
186214

187-
cf_gtr_front_button_pins: cf-gtr-front-button-pins {
188-
marvell,pins = "mpp53";
215+
cf_gtr_switch_reset_pins: cf-gtr-switch-reset-pins {
216+
marvell,pins = "mpp18";
189217
marvell,function = "gpio";
190218
};
191219

192-
cf_gtr_rear_button_pins: cf-gtr-rear-button-pins {
193-
marvell,pins = "mpp36";
220+
cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus {
221+
marvell,pins = "mpp22";
222+
marvell,function = "gpio";
223+
};
224+
225+
cf_gtr_wifi_disable_pins: wifi-disable-pins {
226+
marvell,pins = "mpp30", "mpp31";
194227
marvell,function = "gpio";
195228
};
196229
};
@@ -221,32 +254,39 @@
221254
};
222255

223256
pcie {
257+
pinctrl-0 = <&cf_gtr_pci_pins>;
258+
pinctrl-names = "default";
224259
status = "okay";
225260
/*
226261
* The PCIe units are accessible through
227262
* the mini-PCIe connectors on the board.
228263
*/
264+
/* CON3 - serdes 0 */
229265
pcie@1,0 {
230266
reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
231267
status = "okay";
232268
};
233269

270+
/* CON4 - serdes 2 */
234271
pcie@2,0 {
235272
reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
236273
status = "okay";
237274
};
238275

276+
/* CON2 - serdes 4 */
239277
pcie@3,0 {
240278
reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
241279
status = "okay";
242280
};
243281
};
244282
};
245283

246-
sfp0: sfp {
284+
/* CON5 */
285+
sfp0: sfp-0 {
247286
compatible = "sff,sfp";
287+
pinctrl-0 = <&cf_gtr_sfp0_pins>;
288+
pinctrl-names = "default";
248289
i2c-bus = <&i2c1>;
249-
los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
250290
mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>;
251291
tx-disable-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
252292
};
@@ -273,6 +313,8 @@
273313

274314
gpio-leds {
275315
compatible = "gpio-leds";
316+
pinctrl-0 = <&cf_gtr_led_pins>;
317+
pinctrl-names = "default";
276318

277319
led1 {
278320
function = LED_FUNCTION_CPU;
@@ -408,7 +450,7 @@
408450
};
409451

410452
&gpio0 {
411-
pinctrl-0 = <&cf_gtr_fan_pwm>;
453+
pinctrl-0 = <&cf_gtr_fan_pwm &cf_gtr_wifi_disable_pins>;
412454
pinctrl-names = "default";
413455

414456
wifi-disable {
@@ -420,7 +462,7 @@
420462
};
421463

422464
&gpio1 {
423-
pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins>;
465+
pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins &cf_gtr_lte_disable_pins>;
424466
pinctrl-names = "default";
425467

426468
lte-disable {

arch/arm/boot/dts/marvell/armada-388-clearfog.dts

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,8 +10,9 @@
1010

1111
/ {
1212
model = "SolidRun Clearfog A1";
13-
compatible = "solidrun,clearfog-a1", "marvell,armada388",
14-
"marvell,armada385", "marvell,armada380";
13+
compatible = "solidrun,clearfog-pro-a1", "solidrun,clearfog-a1",
14+
"marvell,armada388", "marvell,armada385",
15+
"marvell,armada380";
1516

1617
soc {
1718
internal-regs {

0 commit comments

Comments
 (0)