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Robert Richterdavejiang
Robert Richter
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davejiang
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cxl: Enable AMD Zen5 address translation using ACPI PRMT
Add AMD Zen5 support for address translation. Zen5 systems may be configured to use 'Normalized addresses'. Then, host physical addresses (HPA) are different from their system physical addresses (SPA). The endpoint has its own physical address space and an incoming HPA is already converted to the device's physical address (DPA). Thus it has interleaving disabled and CXL endpoints are programmed passthrough (DPA == HPA). Host Physical Addresses (HPAs) need to be translated from the endpoint to its CXL host bridge, esp. to identify the endpoint's root decoder and region's address range. ACPI Platform Runtime Mechanism (PRM) provides a handler to translate the DPA to its SPA. This is documented in: AMD Family 1Ah Models 00h–0Fh and Models 10h–1Fh ACPI v6.5 Porting Guide, Publication # 58088 https://www.amd.com/en/search/documentation/hub.html With Normalized Addressing this PRM handler must be used to translate an HPA of an endpoint to its SPA. Do the following to implement AMD Zen5 address translation: Introduce a new file core/atl.c to handle ACPI PRM specific address translation code. Naming is loosely related to the kernel's AMD Address Translation Library (CONFIG_AMD_ATL) but implementation does not depend on it, nor it is vendor specific. Use Kbuild and Kconfig options respectively to enable the code depending on architecture and platform options. AMD Zen5 systems support the ACPI PRM CXL Address Translation firmware call (see ACPI v6.5 Porting Guide, Address Translation - CXL DPA to System Physical Address). Firmware enables the PRM handler if the platform has address translation implemented. Check firmware and kernel support of ACPI PRM using the specific GUID. On success enable address translation by setting up the earlier introduced root port callback, see function cxl_prm_setup_translation(). Setup is done in cxl_setup_prm_address_translation(), it is the only function that needs to be exported. For low level PRM firmware calls, use the ACPI framework. Identify the region's interleaving ways by inspecting the address ranges. Also determine the interleaving granularity using the address translation callback. Note that the position of the chunk from one interleaving block to the next may vary and thus cannot be considered constant. Address offsets larger than the interleaving block size cannot be used to calculate the granularity. Thus, probe the granularity using address translation for various HPAs in the same interleaving block. [ dj: Add atl.o build to cxl_test ] Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Tested-by: Gregory Price <gourry@gourry.net> Signed-off-by: Robert Richter <rrichter@amd.com> Link: https://patch.msgid.link/20260114164837.1076338-11-rrichter@amd.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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‎drivers/cxl/Kconfig‎

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@@ -233,4 +233,9 @@ config CXL_MCE
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def_bool y
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depends on X86_MCE && MEMORY_FAILURE
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config CXL_ATL
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def_bool y
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depends on CXL_REGION
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depends on ACPI_PRMT && AMD_NB
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endif

‎drivers/cxl/acpi.c‎

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@@ -925,6 +925,8 @@ static int cxl_acpi_probe(struct platform_device *pdev)
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cxl_root->ops.qos_class = cxl_acpi_qos_class;
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root_port = &cxl_root->port;
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cxl_setup_prm_address_translation(cxl_root);
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rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
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add_host_bridge_dport);
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if (rc < 0)

‎drivers/cxl/core/Makefile‎

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@@ -20,3 +20,4 @@ cxl_core-$(CONFIG_CXL_REGION) += region.o
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cxl_core-$(CONFIG_CXL_MCE) += mce.o
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cxl_core-$(CONFIG_CXL_FEATURES) += features.o
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cxl_core-$(CONFIG_CXL_EDAC_MEM_FEATURES) += edac.o
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cxl_core-$(CONFIG_CXL_ATL) += atl.o

‎drivers/cxl/core/atl.c‎

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@@ -0,0 +1,190 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2025 Advanced Micro Devices, Inc.
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*/
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#include <linux/prmt.h>
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#include <linux/pci.h>
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#include <linux/acpi.h>
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#include <cxlmem.h>
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#include "core.h"
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/*
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* PRM Address Translation - CXL DPA to System Physical Address
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*
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* Reference:
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*
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* AMD Family 1Ah Models 00h–0Fh and Models 10h–1Fh
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* ACPI v6.5 Porting Guide, Publication # 58088
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*/
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static const guid_t prm_cxl_dpa_spa_guid =
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GUID_INIT(0xee41b397, 0x25d4, 0x452c, 0xad, 0x54, 0x48, 0xc6, 0xe3,
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0x48, 0x0b, 0x94);
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struct prm_cxl_dpa_spa_data {
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u64 dpa;
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u8 reserved;
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u8 devfn;
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u8 bus;
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u8 segment;
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u64 *spa;
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} __packed;
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static u64 prm_cxl_dpa_spa(struct pci_dev *pci_dev, u64 dpa)
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{
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struct prm_cxl_dpa_spa_data data;
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u64 spa;
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int rc;
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data = (struct prm_cxl_dpa_spa_data) {
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.dpa = dpa,
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.devfn = pci_dev->devfn,
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.bus = pci_dev->bus->number,
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.segment = pci_domain_nr(pci_dev->bus),
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.spa = &spa,
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};
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rc = acpi_call_prm_handler(prm_cxl_dpa_spa_guid, &data);
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if (rc) {
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pci_dbg(pci_dev, "failed to get SPA for %#llx: %d\n", dpa, rc);
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return ULLONG_MAX;
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}
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pci_dbg(pci_dev, "PRM address translation: DPA -> SPA: %#llx -> %#llx\n", dpa, spa);
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return spa;
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}
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static int cxl_prm_setup_root(struct cxl_root *cxl_root, void *data)
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{
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struct cxl_region_context *ctx = data;
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struct cxl_endpoint_decoder *cxled = ctx->cxled;
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struct cxl_decoder *cxld = &cxled->cxld;
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struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
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struct range hpa_range = ctx->hpa_range;
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struct pci_dev *pci_dev;
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u64 spa_len, len;
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u64 addr, base_spa, base;
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int ways, gran;
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/*
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* When Normalized Addressing is enabled, the endpoint maintains a 1:1
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* mapping between HPA and DPA. If disabled, skip address translation
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* and perform only a range check.
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*/
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if (hpa_range.start != cxled->dpa_res->start)
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return 0;
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/*
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* Endpoints are programmed passthrough in Normalized Addressing mode.
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*/
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if (ctx->interleave_ways != 1) {
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dev_dbg(&cxld->dev, "unexpected interleaving config: ways: %d granularity: %d\n",
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ctx->interleave_ways, ctx->interleave_granularity);
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return -ENXIO;
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}
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if (!cxlmd || !dev_is_pci(cxlmd->dev.parent)) {
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dev_dbg(&cxld->dev, "No endpoint found: %s, range %#llx-%#llx\n",
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dev_name(cxld->dev.parent), hpa_range.start,
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hpa_range.end);
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return -ENXIO;
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}
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pci_dev = to_pci_dev(cxlmd->dev.parent);
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/* Translate HPA range to SPA. */
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base = hpa_range.start;
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hpa_range.start = prm_cxl_dpa_spa(pci_dev, hpa_range.start);
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hpa_range.end = prm_cxl_dpa_spa(pci_dev, hpa_range.end);
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base_spa = hpa_range.start;
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if (hpa_range.start == ULLONG_MAX || hpa_range.end == ULLONG_MAX) {
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dev_dbg(cxld->dev.parent,
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"CXL address translation: Failed to translate HPA range: %#llx-%#llx:%#llx-%#llx(%s)\n",
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hpa_range.start, hpa_range.end, ctx->hpa_range.start,
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ctx->hpa_range.end, dev_name(&cxld->dev));
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return -ENXIO;
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}
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/*
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* Since translated addresses include the interleaving offsets, align
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* the range to 256 MB.
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*/
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hpa_range.start = ALIGN_DOWN(hpa_range.start, SZ_256M);
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hpa_range.end = ALIGN(hpa_range.end, SZ_256M) - 1;
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len = range_len(&ctx->hpa_range);
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spa_len = range_len(&hpa_range);
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if (!len || !spa_len || spa_len % len) {
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dev_dbg(cxld->dev.parent,
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"CXL address translation: HPA range not contiguous: %#llx-%#llx:%#llx-%#llx(%s)\n",
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hpa_range.start, hpa_range.end, ctx->hpa_range.start,
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ctx->hpa_range.end, dev_name(&cxld->dev));
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return -ENXIO;
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}
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ways = spa_len / len;
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gran = SZ_256;
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/*
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* Determine interleave granularity
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*
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* Note: The position of the chunk from one interleaving block to the
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* next may vary and thus cannot be considered constant. Address offsets
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* larger than the interleaving block size cannot be used to calculate
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* the granularity.
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*/
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if (ways > 1) {
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while (gran <= SZ_16M) {
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addr = prm_cxl_dpa_spa(pci_dev, base + gran);
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if (addr != base_spa + gran)
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break;
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gran <<= 1;
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}
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}
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if (gran > SZ_16M) {
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dev_dbg(cxld->dev.parent,
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"CXL address translation: Cannot determine granularity: %#llx-%#llx:%#llx-%#llx(%s)\n",
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hpa_range.start, hpa_range.end, ctx->hpa_range.start,
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ctx->hpa_range.end, dev_name(&cxld->dev));
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return -ENXIO;
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}
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ctx->hpa_range = hpa_range;
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ctx->interleave_ways = ways;
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ctx->interleave_granularity = gran;
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dev_dbg(&cxld->dev,
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"address mapping found for %s (hpa -> spa): %#llx+%#llx -> %#llx+%#llx ways:%d granularity:%d\n",
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dev_name(cxlmd->dev.parent), base, len, hpa_range.start,
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spa_len, ways, gran);
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return 0;
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}
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void cxl_setup_prm_address_translation(struct cxl_root *cxl_root)
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{
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struct device *host = cxl_root->port.uport_dev;
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u64 spa;
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struct prm_cxl_dpa_spa_data data = { .spa = &spa };
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int rc;
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/*
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* Applies only to PCIe Host Bridges which are children of the CXL Root
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* Device (HID=“ACPI0017”). Check this and drop cxl_test instances.
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*/
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if (!acpi_match_device(host->driver->acpi_match_table, host))
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return;
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/* Check kernel (-EOPNOTSUPP) and firmware support (-ENODEV) */
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rc = acpi_call_prm_handler(prm_cxl_dpa_spa_guid, &data);
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if (rc == -EOPNOTSUPP || rc == -ENODEV)
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return;
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cxl_root->ops.translation_setup_root = cxl_prm_setup_root;
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}
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EXPORT_SYMBOL_NS_GPL(cxl_setup_prm_address_translation, "CXL");

‎drivers/cxl/cxl.h‎

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@@ -817,6 +817,13 @@ static inline void cxl_dport_init_ras_reporting(struct cxl_dport *dport,
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struct device *host) { }
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#endif
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#ifdef CONFIG_CXL_ATL
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void cxl_setup_prm_address_translation(struct cxl_root *cxl_root);
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#else
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static inline
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void cxl_setup_prm_address_translation(struct cxl_root *cxl_root) {}
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#endif
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struct cxl_decoder *to_cxl_decoder(struct device *dev);
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struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev);
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struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev);

‎tools/testing/cxl/Kbuild‎

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@@ -63,6 +63,7 @@ cxl_core-$(CONFIG_CXL_REGION) += $(CXL_CORE_SRC)/region.o
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cxl_core-$(CONFIG_CXL_MCE) += $(CXL_CORE_SRC)/mce.o
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cxl_core-$(CONFIG_CXL_FEATURES) += $(CXL_CORE_SRC)/features.o
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cxl_core-$(CONFIG_CXL_EDAC_MEM_FEATURES) += $(CXL_CORE_SRC)/edac.o
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cxl_core-$(CONFIG_CXL_ATL) += $(CXL_CORE_SRC)/atl.o
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cxl_core-y += config_check.o
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cxl_core-y += cxl_core_test.o
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cxl_core-y += cxl_core_exports.o

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