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hte: Add Tegra234 provider
The Tegra234 AON GPIO instance and LIC IRQ support HTE. For the GPIO HTE support, it also requires to add mapping between GPIO and HTE framework same as it was done with Tegra194 SoC. Signed-off-by: Dipen Patel <dipenp@nvidia.com>
1 parent 59cc80a commit b003fb5

2 files changed

Lines changed: 121 additions & 5 deletions

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‎drivers/hte/hte-tegra194-test.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616
#include <linux/hte.h>
1717

1818
/*
19-
* This sample HTE GPIO test driver demonstrates HTE API usage by enabling
19+
* This sample HTE test driver demonstrates HTE API usage by enabling
2020
* hardware timestamp on gpio_in and specified LIC IRQ lines.
2121
*
2222
* Note: gpio_out and gpio_in need to be shorted externally in order for this

‎drivers/hte/hte-tegra194.c‎

Lines changed: 120 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -62,6 +62,10 @@
6262
#define NV_AON_HTE_SLICE2_IRQ_GPIO_25 25
6363
#define NV_AON_HTE_SLICE2_IRQ_GPIO_26 26
6464
#define NV_AON_HTE_SLICE2_IRQ_GPIO_27 27
65+
#define NV_AON_HTE_SLICE2_IRQ_GPIO_28 28
66+
#define NV_AON_HTE_SLICE2_IRQ_GPIO_29 29
67+
#define NV_AON_HTE_SLICE2_IRQ_GPIO_30 30
68+
#define NV_AON_HTE_SLICE2_IRQ_GPIO_31 31
6569

6670
#define HTE_TECTRL 0x0
6771
#define HTE_TETSCH 0x4
@@ -220,14 +224,115 @@ static const struct tegra_hte_line_mapped tegra194_aon_gpio_sec_map[] = {
220224
[39] = {NV_AON_SLICE_INVALID, 0},
221225
};
222226

223-
static const struct tegra_hte_data aon_hte = {
227+
static const struct tegra_hte_line_mapped tegra234_aon_gpio_map[] = {
228+
/* gpio, slice, bit_index */
229+
/* AA port */
230+
[0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11},
231+
[1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10},
232+
[2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9},
233+
[3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8},
234+
[4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7},
235+
[5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6},
236+
[6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5},
237+
[7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4},
238+
/* BB port */
239+
[8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3},
240+
[9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2},
241+
[10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1},
242+
[11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0},
243+
/* CC port */
244+
[12] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22},
245+
[13] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21},
246+
[14] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20},
247+
[15] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19},
248+
[16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18},
249+
[17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17},
250+
[18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16},
251+
[19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15},
252+
/* DD port */
253+
[20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14},
254+
[21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13},
255+
[22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12},
256+
/* EE port */
257+
[23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31},
258+
[24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30},
259+
[25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29},
260+
[26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28},
261+
[27] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27},
262+
[28] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26},
263+
[29] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25},
264+
[30] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24},
265+
/* GG port */
266+
[31] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23},
267+
};
268+
269+
static const struct tegra_hte_line_mapped tegra234_aon_gpio_sec_map[] = {
270+
/* gpio, slice, bit_index */
271+
/* AA port */
272+
[0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11},
273+
[1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10},
274+
[2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9},
275+
[3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8},
276+
[4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7},
277+
[5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6},
278+
[6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5},
279+
[7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4},
280+
/* BB port */
281+
[8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3},
282+
[9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2},
283+
[10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1},
284+
[11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0},
285+
[12] = {NV_AON_SLICE_INVALID, 0},
286+
[13] = {NV_AON_SLICE_INVALID, 0},
287+
[14] = {NV_AON_SLICE_INVALID, 0},
288+
[15] = {NV_AON_SLICE_INVALID, 0},
289+
/* CC port */
290+
[16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22},
291+
[17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21},
292+
[18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20},
293+
[19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19},
294+
[20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18},
295+
[21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17},
296+
[22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16},
297+
[23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15},
298+
/* DD port */
299+
[24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14},
300+
[25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13},
301+
[26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12},
302+
[27] = {NV_AON_SLICE_INVALID, 0},
303+
[28] = {NV_AON_SLICE_INVALID, 0},
304+
[29] = {NV_AON_SLICE_INVALID, 0},
305+
[30] = {NV_AON_SLICE_INVALID, 0},
306+
[31] = {NV_AON_SLICE_INVALID, 0},
307+
/* EE port */
308+
[32] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31},
309+
[33] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30},
310+
[34] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29},
311+
[35] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28},
312+
[36] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27},
313+
[37] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26},
314+
[38] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25},
315+
[39] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24},
316+
/* GG port */
317+
[40] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23},
318+
};
319+
320+
static const struct tegra_hte_data t194_aon_hte = {
224321
.map_sz = ARRAY_SIZE(tegra194_aon_gpio_map),
225322
.map = tegra194_aon_gpio_map,
226323
.sec_map_sz = ARRAY_SIZE(tegra194_aon_gpio_sec_map),
227324
.sec_map = tegra194_aon_gpio_sec_map,
228325
.type = HTE_TEGRA_TYPE_GPIO,
229326
};
230327

328+
static const struct tegra_hte_data t234_aon_hte = {
329+
.map_sz = ARRAY_SIZE(tegra234_aon_gpio_map),
330+
.map = tegra234_aon_gpio_map,
331+
.sec_map_sz = ARRAY_SIZE(tegra234_aon_gpio_sec_map),
332+
.sec_map = tegra234_aon_gpio_sec_map,
333+
.type = HTE_TEGRA_TYPE_GPIO,
334+
};
335+
231336
static const struct tegra_hte_data lic_hte = {
232337
.map_sz = 0,
233338
.map = NULL,
@@ -535,7 +640,9 @@ static bool tegra_hte_match_from_linedata(const struct hte_chip *chip,
535640

536641
static const struct of_device_id tegra_hte_of_match[] = {
537642
{ .compatible = "nvidia,tegra194-gte-lic", .data = &lic_hte},
538-
{ .compatible = "nvidia,tegra194-gte-aon", .data = &aon_hte},
643+
{ .compatible = "nvidia,tegra194-gte-aon", .data = &t194_aon_hte},
644+
{ .compatible = "nvidia,tegra234-gte-lic", .data = &lic_hte},
645+
{ .compatible = "nvidia,tegra234-gte-aon", .data = &t234_aon_hte},
539646
{ }
540647
};
541648
MODULE_DEVICE_TABLE(of, tegra_hte_of_match);
@@ -635,8 +742,17 @@ static int tegra_hte_probe(struct platform_device *pdev)
635742

636743
gc->match_from_linedata = tegra_hte_match_from_linedata;
637744

638-
hte_dev->c = gpiochip_find("tegra194-gpio-aon",
639-
tegra_get_gpiochip_from_name);
745+
if (of_device_is_compatible(dev->of_node,
746+
"nvidia,tegra194-gte-aon"))
747+
hte_dev->c = gpiochip_find("tegra194-gpio-aon",
748+
tegra_get_gpiochip_from_name);
749+
else if (of_device_is_compatible(dev->of_node,
750+
"nvidia,tegra234-gte-aon"))
751+
hte_dev->c = gpiochip_find("tegra234-gpio-aon",
752+
tegra_get_gpiochip_from_name);
753+
else
754+
return -ENODEV;
755+
640756
if (!hte_dev->c)
641757
return dev_err_probe(dev, -EPROBE_DEFER,
642758
"wait for gpio controller\n");

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