Skip to content

Commit b00ed48

Browse files
torvaldstorvalds
committed
Merge tag 'dmaengine-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
Pull dmaengine updates from Vinod Koul: "Nothing special, this includes a couple of new device support and new driver support and bunch of driver updates. New support: - Tegra gpcdma driver support - Qualcomm SM8350, Sm8450 and SC7280 device support - Renesas RZN1 dma and platform support Updates: - stm32 device pause/resume support and updates - DMA memset ops Documentation and usage clarification - deprecate '#dma-channels' & '#dma-requests' bindings - driver updates for stm32, ptdma idsx etc" * tag 'dmaengine-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (87 commits) dmaengine: idxd: make idxd_wq_enable() return 0 if wq is already enabled dmaengine: sun6i: Add support for the D1 variant dmaengine: sun6i: Add support for 34-bit physical addresses dmaengine: sun6i: Do not use virt_to_phys dt-bindings: dma: sun50i-a64: Add compatible for D1 dmaengine: tegra: Remove unused switch case dmaengine: tegra: Fix uninitialized variable usage dmaengine: stm32-dma: add device_pause/device_resume support dmaengine: stm32-dma: rename pm ops before dma pause/resume introduction dmaengine: stm32-dma: pass DMA_SxSCR value to stm32_dma_handle_chan_done() dmaengine: stm32-dma: introduce stm32_dma_sg_inc to manage chan->next_sg dmaengine: stm32-dmamux: avoid reset of dmamux if used by coprocessor dmaengine: qcom: gpi: Add support for sc7280 dt-bindings: dma: pl330: Add power-domains dmaengine: stm32-mdma: use dev_dbg on non-busy channel spurious it dmaengine: stm32-mdma: fix chan initialization in stm32_mdma_irq_handler() dmaengine: stm32-mdma: remove GISR1 register dmaengine: ti: deprecate '#dma-channels' dmaengine: mmp: deprecate '#dma-channels' dmaengine: pxa: deprecate '#dma-channels' and '#dma-requests' ...
2 parents c3a9a3c + d1a2859 commit b00ed48

64 files changed

Lines changed: 2744 additions & 349 deletions

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

‎Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.yaml‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,17 @@ properties:
3939
'#power-domain-cells':
4040
const: 0
4141

42+
'#address-cells':
43+
const: 1
44+
45+
'#size-cells':
46+
const: 1
47+
48+
patternProperties:
49+
"^dma-router@[a-f0-9]+$":
50+
type: object
51+
$ref: "../dma/renesas,rzn1-dmamux.yaml#"
52+
4253
required:
4354
- compatible
4455
- reg

‎Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml‎

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -20,9 +20,11 @@ properties:
2020

2121
compatible:
2222
oneOf:
23-
- const: allwinner,sun50i-a64-dma
24-
- const: allwinner,sun50i-a100-dma
25-
- const: allwinner,sun50i-h6-dma
23+
- enum:
24+
- allwinner,sun20i-d1-dma
25+
- allwinner,sun50i-a64-dma
26+
- allwinner,sun50i-a100-dma
27+
- allwinner,sun50i-h6-dma
2628
- items:
2729
- const: allwinner,sun8i-r40-dma
2830
- const: allwinner,sun50i-a64-dma
@@ -58,6 +60,7 @@ if:
5860
properties:
5961
compatible:
6062
enum:
63+
- allwinner,sun20i-d1-dma
6164
- allwinner,sun50i-a100-dma
6265
- allwinner,sun50i-h6-dma
6366

‎Documentation/devicetree/bindings/dma/altr,msgdma.yaml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
77
title: Altera mSGDMA IP core
88

99
maintainers:
10-
- Olivier Dautricourt <olivier.dautricourt@orolia.com>
10+
- Olivier Dautricourt <olivierdautricourt@gmail.com>
1111

1212
description: |
1313
Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA)

‎Documentation/devicetree/bindings/dma/arm,pl330.yaml‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -55,6 +55,9 @@ properties:
5555

5656
dma-coherent: true
5757

58+
power-domains:
59+
maxItems: 1
60+
5861
resets:
5962
minItems: 1
6063
maxItems: 2

‎Documentation/devicetree/bindings/dma/mmp-dma.txt‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -10,10 +10,12 @@ Required properties:
1010
or one irq for pdma device
1111

1212
Optional properties:
13-
- #dma-channels: Number of DMA channels supported by the controller (defaults
13+
- dma-channels: Number of DMA channels supported by the controller (defaults
1414
to 32 when not specified)
15-
- #dma-requests: Number of DMA requestor lines supported by the controller
15+
- #dma-channels: deprecated
16+
- dma-requests: Number of DMA requestor lines supported by the controller
1617
(defaults to 32 when not specified)
18+
- #dma-requests: deprecated
1719

1820
"marvell,pdma-1.0"
1921
Used platforms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688.
@@ -33,7 +35,7 @@ pdma: dma-controller@d4000000 {
3335
reg = <0xd4000000 0x10000>;
3436
interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
3537
interrupt-parent = <&intcmux32>;
36-
#dma-channels = <16>;
38+
dma-channels = <16>;
3739
};
3840

3941
/*
@@ -45,7 +47,7 @@ pdma: dma-controller@d4000000 {
4547
compatible = "marvell,pdma-1.0";
4648
reg = <0xd4000000 0x10000>;
4749
interrupts = <47>;
48-
#dma-channels = <16>;
50+
dma-channels = <16>;
4951
};
5052

5153

‎Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml‎

Lines changed: 110 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,110 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/dma/nvidia,tegra186-gpc-dma.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: NVIDIA Tegra GPC DMA Controller Device Tree Bindings
8+
9+
description: |
10+
The Tegra General Purpose Central (GPC) DMA controller is used for faster
11+
data transfers between memory to memory, memory to device and device to
12+
memory.
13+
14+
maintainers:
15+
- Jon Hunter <jonathanh@nvidia.com>
16+
- Rajesh Gumasta <rgumasta@nvidia.com>
17+
18+
allOf:
19+
- $ref: "dma-controller.yaml#"
20+
21+
properties:
22+
compatible:
23+
oneOf:
24+
- const: nvidia,tegra186-gpcdma
25+
- items:
26+
- const: nvidia,tegra194-gpcdma
27+
- const: nvidia,tegra186-gpcdma
28+
29+
"#dma-cells":
30+
const: 1
31+
32+
reg:
33+
maxItems: 1
34+
35+
interrupts:
36+
description:
37+
Should contain all of the per-channel DMA interrupts in
38+
ascending order with respect to the DMA channel index.
39+
minItems: 1
40+
maxItems: 31
41+
42+
resets:
43+
maxItems: 1
44+
45+
reset-names:
46+
const: gpcdma
47+
48+
iommus:
49+
maxItems: 1
50+
51+
dma-coherent: true
52+
53+
required:
54+
- compatible
55+
- reg
56+
- interrupts
57+
- resets
58+
- reset-names
59+
- "#dma-cells"
60+
- iommus
61+
62+
additionalProperties: false
63+
64+
examples:
65+
- |
66+
#include <dt-bindings/interrupt-controller/arm-gic.h>
67+
#include <dt-bindings/memory/tegra186-mc.h>
68+
#include <dt-bindings/reset/tegra186-reset.h>
69+
70+
dma-controller@2600000 {
71+
compatible = "nvidia,tegra186-gpcdma";
72+
reg = <0x2600000 0x210000>;
73+
resets = <&bpmp TEGRA186_RESET_GPCDMA>;
74+
reset-names = "gpcdma";
75+
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
76+
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
77+
<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
78+
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
79+
<GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
80+
<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
81+
<GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
82+
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
83+
<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
84+
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
85+
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
86+
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
87+
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
88+
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
89+
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
90+
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
91+
<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
92+
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
93+
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
94+
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
95+
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
96+
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
97+
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
98+
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
99+
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
100+
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
101+
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
102+
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
103+
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
104+
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
105+
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
106+
#dma-cells = <1>;
107+
iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
108+
dma-coherent;
109+
};
110+
...

‎Documentation/devicetree/bindings/dma/qcom,gpi.yaml‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,9 +19,12 @@ allOf:
1919
properties:
2020
compatible:
2121
enum:
22+
- qcom,sc7280-gpi-dma
2223
- qcom,sdm845-gpi-dma
2324
- qcom,sm8150-gpi-dma
2425
- qcom,sm8250-gpi-dma
26+
- qcom,sm8350-gpi-dma
27+
- qcom,sm8450-gpi-dma
2528

2629
reg:
2730
maxItems: 1

‎Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml‎

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -42,11 +42,10 @@ properties:
4242
- const: renesas,rcar-dmac
4343

4444
- items:
45-
- const: renesas,dmac-r8a779a0 # R-Car V3U
46-
47-
- items:
48-
- const: renesas,dmac-r8a779f0 # R-Car S4-8
49-
- const: renesas,rcar-gen4-dmac
45+
- enum:
46+
- renesas,dmac-r8a779a0 # R-Car V3U
47+
- renesas,dmac-r8a779f0 # R-Car S4-8
48+
- const: renesas,rcar-gen4-dmac # R-Car Gen4
5049

5150
reg: true
5251

@@ -121,7 +120,6 @@ if:
121120
compatible:
122121
contains:
123122
enum:
124-
- renesas,dmac-r8a779a0
125123
- renesas,rcar-gen4-dmac
126124
then:
127125
properties:

‎Documentation/devicetree/bindings/dma/renesas,rzn1-dmamux.yaml‎

Lines changed: 51 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,51 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/dma/renesas,rzn1-dmamux.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Renesas RZ/N1 DMA mux
8+
9+
maintainers:
10+
- Miquel Raynal <miquel.raynal@bootlin.com>
11+
12+
allOf:
13+
- $ref: "dma-router.yaml#"
14+
15+
properties:
16+
compatible:
17+
const: renesas,rzn1-dmamux
18+
19+
reg:
20+
maxItems: 1
21+
description: DMA mux first register offset within the system control parent.
22+
23+
'#dma-cells':
24+
const: 6
25+
description:
26+
The first four cells are dedicated to the master DMA controller. The fifth
27+
cell gives the DMA mux bit index that must be set starting from 0. The
28+
sixth cell gives the binary value that must be written there, ie. 0 or 1.
29+
30+
dma-masters:
31+
minItems: 1
32+
maxItems: 2
33+
34+
dma-requests:
35+
const: 32
36+
37+
required:
38+
- reg
39+
- dma-requests
40+
41+
additionalProperties: false
42+
43+
examples:
44+
- |
45+
dma-router@a0 {
46+
compatible = "renesas,rzn1-dmamux";
47+
reg = <0xa0 4>;
48+
#dma-cells = <6>;
49+
dma-masters = <&dma0 &dma1>;
50+
dma-requests = <32>;
51+
};

‎Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml‎

Lines changed: 17 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,15 @@ allOf:
2828
properties:
2929
compatible:
3030
items:
31-
- const: sifive,fu540-c000-pdma
31+
- enum:
32+
- sifive,fu540-c000-pdma
33+
- const: sifive,pdma0
34+
description:
35+
Should be "sifive,<chip>-pdma" and "sifive,pdma<version>".
36+
Supported compatible strings are -
37+
"sifive,fu540-c000-pdma" for the SiFive PDMA v0 as integrated onto the
38+
SiFive FU540 chip resp and "sifive,pdma0" for the SiFive PDMA v0 IP block
39+
with no chip integration tweaks.
3240

3341
reg:
3442
maxItems: 1
@@ -37,6 +45,12 @@ properties:
3745
minItems: 1
3846
maxItems: 8
3947

48+
dma-channels:
49+
description: For backwards-compatibility, the default value is 4
50+
minimum: 1
51+
maximum: 4
52+
default: 4
53+
4054
'#dma-cells':
4155
const: 1
4256

@@ -50,8 +64,9 @@ unevaluatedProperties: false
5064
examples:
5165
- |
5266
dma-controller@3000000 {
53-
compatible = "sifive,fu540-c000-pdma";
67+
compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
5468
reg = <0x3000000 0x8000>;
69+
dma-channels = <4>;
5570
interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, <30>;
5671
#dma-cells = <1>;
5772
};

0 commit comments

Comments
 (0)