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Yu-Chun Linarndb
Yu-Chun Lin
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arm64: dts: realtek: Add Kent SoC and EVB device trees
Add Device Tree hierarchy for Realtek Kent SoC family: - kent.dtsi: base SoC layer - rtd<variant>.dtsi: SoC variant layer - rtd<variant>-<board>.dtsi: board layer - rtd<variant>-<board>-<config>.dts: board configuration layer Include RTD1501s Phantom EVB (8GB), RTD1861B Krypton EVB (8GB), and RTD1920s Smallville EVB (4GB). Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20260127071530.25426-3-eleanor15x@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
1 parent d83bcab commit b095c27

11 files changed

Lines changed: 596 additions & 4 deletions

‎arch/arm64/boot/dts/realtek/Makefile‎

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# SPDX-License-Identifier: GPL-2.0-only
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dtb-$(CONFIG_ARCH_REALTEK) += rtd1293-ds418j.dtb
4-
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dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-mele-v9.dtb
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dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-probox2-ava.dtb
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dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-xnano-x5.dtb
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dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-zidoo-x9s.dtb
9-
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dtb-$(CONFIG_ARCH_REALTEK) += rtd1296-ds418.dtb
11-
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dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-bpi-m4.dtb
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dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-lionskin.dtb
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dtb-$(CONFIG_ARCH_REALTEK) += rtd1501s-phantom-8gb.dtb
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dtb-$(CONFIG_ARCH_REALTEK) += rtd1619-mjolnir.dtb
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dtb-$(CONFIG_ARCH_REALTEK) += rtd1861b-krypton-8gb.dtb
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dtb-$(CONFIG_ARCH_REALTEK) += rtd1920s-smallville-4gb.dtb

‎arch/arm64/boot/dts/realtek/kent.dtsi‎

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Realtek Kent SoC family
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*
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* Copyright (c) 2024 Realtek Semiconductor Corp.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &uart0;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a78";
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reg = <0x0>;
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enable-method = "psci";
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next-level-cache = <&l2_0>;
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dynamic-power-coefficient = <454>;
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#cooling-cells = <2>;
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l2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-line-size = <64>;
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cache-sets = <256>;
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cache-size = <0x40000>;
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cache-unified;
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next-level-cache = <&l3>;
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};
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};
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cpu1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a78";
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reg = <0x100>;
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enable-method = "psci";
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next-level-cache = <&l2_1>;
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dynamic-power-coefficient = <454>;
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#cooling-cells = <2>;
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l2_1: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-line-size = <64>;
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cache-sets = <256>;
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cache-size = <0x40000>;
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cache-unified;
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next-level-cache = <&l3>;
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};
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};
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cpu2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a78";
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reg = <0x200>;
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enable-method = "psci";
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next-level-cache = <&l2_2>;
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dynamic-power-coefficient = <454>;
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#cooling-cells = <2>;
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l2_2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-line-size = <64>;
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cache-sets = <256>;
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cache-size = <0x40000>;
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cache-unified;
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next-level-cache = <&l3>;
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};
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};
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cpu3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a78";
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reg = <0x300>;
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enable-method = "psci";
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next-level-cache = <&l2_3>;
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dynamic-power-coefficient = <454>;
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#cooling-cells = <2>;
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l2_3: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-line-size = <64>;
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cache-sets = <256>;
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cache-size = <0x40000>;
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cache-unified;
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next-level-cache = <&l3>;
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};
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};
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l3: l3-cache {
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compatible = "cache";
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cache-level = <3>;
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cache-line-size = <64>;
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cache-sets = <512>;
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cache-size = <0x200000>;
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cache-unified;
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};
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};
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psci: psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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soc@0 {
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compatible = "simple-bus";
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ranges = <0x0 0x0 0x0 0x40000>, /* boot code */
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<0x98000000 0x0 0x98000000 0xef0000>, /* rbus */
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<0xa0000000 0x0 0xa0000000 0x10000000>, /* PCIE */
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<0xff000000 0x0 0xff000000 0x200000>; /* GIC */
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#address-cells = <1>;
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#size-cells = <1>;
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rbus: bus@98000000 {
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compatible = "simple-bus";
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ranges = <0x0 0x98000000 0xef0000>,
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<0xa0000000 0xa0000000 0x10000000>; /* PCIE */
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#address-cells = <1>;
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#size-cells = <1>;
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uart0: serial@7800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x7800 0x100>;
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clock-frequency = <432000000>;
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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};
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gic: interrupt-controller@ff100000 {
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compatible = "arm,gic-v3";
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reg = <0xff100000 0x10000>,
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<0xff140000 0x80000>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#interrupt-cells = <3>;
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#size-cells = <1>;
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};
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};
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};

‎arch/arm64/boot/dts/realtek/rtd1501.dtsi‎

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Realtek RTD1501 SoC
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*
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* Copyright (c) 2024 Realtek Semiconductor Corp.
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*/
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#include "kent.dtsi"
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&uart0 {
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status = "okay";
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};

‎arch/arm64/boot/dts/realtek/rtd1501s-phantom-8gb.dts‎

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Realtek RTD1501S Phantom EVB
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*
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* Copyright (c) 2024 Realtek Semiconductor Corp.
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*/
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/dts-v1/;
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#include "rtd1501s-phantom.dtsi"
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/ {
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compatible = "realtek,phantom", "realtek,rtd1501s";
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model = "Realtek Phantom EVB Chromium (8GB)";
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memory@40000 {
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device_type = "memory";
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reg = <0x0 0x50000 0x0 0x7ffb0000>,
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<0x0 0x8a100000 0x0 0xdef0000>,
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<0x0 0x98700000 0x0 0x7900000>,
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<0x0 0xa0600000 0x0 0x5ea00000>,
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<0x1 0x0 0x0 0xa0000000>,
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<0x1 0xa0600000 0x0 0x5fa00000>;
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};
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};

‎arch/arm64/boot/dts/realtek/rtd1501s-phantom.dtsi‎

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Realtek RTD1501S Phantom EVB
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*
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* Copyright (c) 2024 Realtek Semiconductor Corp.
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*/
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/dts-v1/;
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#include <dt-bindings/thermal/thermal.h>
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#include "rtd1501.dtsi"
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/ {
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chosen {
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stdout-path = "serial0:460800n8";
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};
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reserved_memory: reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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linux,cma {
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compatible = "shared-dma-pool";
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alignment = <0x0 0x400000>;
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alloc-ranges = <0x0 0x0 0x0 0x20000000>;
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size = <0x0 0x2000000>;
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reusable;
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linux,cma-default;
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};
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};
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cpu_opps: opp-table-cpu {
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compatible = "operating-points-v2";
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opp-shared;
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opp800: opp-800000000 {
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opp-hz = /bits/ 64 <800000000>;
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opp-microvolt = <830000 830000 1100000>;
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};
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opp900: opp-900000000 {
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opp-hz = /bits/ 64 <900000000>;
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opp-microvolt = <850000 850000 1100000>;
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};
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opp1000: opp-1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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opp-microvolt = <870000 870000 1100000>;
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};
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opp1100: opp-1100000000 {
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opp-hz = /bits/ 64 <1100000000>;
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opp-microvolt = <890000 890000 1100000>;
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};
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opp1200: opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <910000 910000 1100000>;
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};
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opp1300: opp-1300000000 {
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opp-hz = /bits/ 64 <1300000000>;
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opp-microvolt = <930000 930000 1100000>;
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};
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opp1400: opp-1400000000 {
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opp-hz = /bits/ 64 <1400000000>;
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opp-microvolt = <950000 950000 1100000>;
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};
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opp1500: opp-1500000000 {
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opp-hz = /bits/ 64 <1500000000>;
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opp-microvolt = <970000 970000 1100000>;
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};
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opp1600: opp-1600000000 {
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opp-hz = /bits/ 64 <1600000000>;
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opp-microvolt = <990000 990000 1100000>;
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opp-suspend;
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};
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opp1700: opp-1700000000 {
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opp-hz = /bits/ 64 <1700000000>;
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opp-microvolt = <1010000 1010000 1100000>;
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};
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opp1800: opp-1800000000 {
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opp-hz = /bits/ 64 <1800000000>;
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opp-microvolt = <1030000 1030000 1100000>;
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};
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opp1900: opp-1900000000 {
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opp-hz = /bits/ 64 <1900000000>;
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opp-microvolt = <1050000 1050000 1100000>;
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};
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};
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};
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&cpu0 {
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operating-points-v2 = <&cpu_opps>;
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#cooling-cells = <2>;
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};
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&cpu1 {
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operating-points-v2 = <&cpu_opps>;
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#cooling-cells = <2>;
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};
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&cpu2 {
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operating-points-v2 = <&cpu_opps>;
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#cooling-cells = <2>;
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};
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&cpu3 {
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operating-points-v2 = <&cpu_opps>;
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#cooling-cells = <2>;
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};

‎arch/arm64/boot/dts/realtek/rtd1861.dtsi‎

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Realtek RTD1861 SoC
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*
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* Copyright (c) 2024 Realtek Semiconductor Corp.
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*/
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8+
#include "kent.dtsi"
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&uart0 {
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status = "okay";
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};

‎arch/arm64/boot/dts/realtek/rtd1861b-krypton-8gb.dts‎

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Realtek RTD1861B Krypton EVB
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*
5+
* Copyright (c) 2024 Realtek Semiconductor Corp.
6+
*/
7+
8+
/dts-v1/;
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#include "rtd1861b-krypton.dtsi"
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/ {
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compatible = "realtek,krypton", "realtek,rtd1861b";
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model = "Realtek Krypton EVB (8GB)";
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memory@40000 {
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device_type = "memory";
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reg = <0x0 0x50000 0x0 0x7ffb0000>,
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<0x0 0x8a100000 0x0 0xdef0000>,
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<0x0 0x98700000 0x0 0x7900000>,
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<0x0 0xa0600000 0x0 0x5ea00000>,
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<0x1 0x0 0x0 0xa0000000>,
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<0x1 0xa0600000 0x0 0x5fa00000>;
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};
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};

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