@@ -1091,7 +1091,7 @@ static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, u32 pasid,
10911091}
10921092
10931093static void build_complete_ppr (struct iommu_cmd * cmd , u16 devid , u32 pasid ,
1094- int status , int tag , bool gn )
1094+ int status , int tag , u8 gn )
10951095{
10961096 memset (cmd , 0 , sizeof (* cmd ));
10971097
@@ -1314,7 +1314,7 @@ static int device_flush_iotlb(struct iommu_dev_data *dev_data,
13141314 struct iommu_cmd cmd ;
13151315 int qdep ;
13161316
1317- qdep = dev_data -> ats . qdep ;
1317+ qdep = dev_data -> ats_qdep ;
13181318 iommu = rlookup_amd_iommu (dev_data -> dev );
13191319 if (!iommu )
13201320 return - EINVAL ;
@@ -1365,7 +1365,7 @@ static int device_flush_dte(struct iommu_dev_data *dev_data)
13651365 return ret ;
13661366 }
13671367
1368- if (dev_data -> ats . enabled )
1368+ if (dev_data -> ats_enabled )
13691369 ret = device_flush_iotlb (dev_data , 0 , ~0UL );
13701370
13711371 return ret ;
@@ -1398,7 +1398,7 @@ static void __domain_flush_pages(struct protection_domain *domain,
13981398
13991399 list_for_each_entry (dev_data , & domain -> dev_list , list ) {
14001400
1401- if (!dev_data -> ats . enabled )
1401+ if (!dev_data -> ats_enabled )
14021402 continue ;
14031403
14041404 ret |= device_flush_iotlb (dev_data , address , size );
@@ -1718,7 +1718,7 @@ static void do_attach(struct iommu_dev_data *dev_data,
17181718 iommu = rlookup_amd_iommu (dev_data -> dev );
17191719 if (!iommu )
17201720 return ;
1721- ats = dev_data -> ats . enabled ;
1721+ ats = dev_data -> ats_enabled ;
17221722
17231723 /* Update data structures */
17241724 dev_data -> domain = domain ;
@@ -1856,14 +1856,14 @@ static int attach_device(struct device *dev,
18561856 if (pdev_pri_ats_enable (pdev ) != 0 )
18571857 goto out ;
18581858
1859- dev_data -> ats . enabled = true ;
1860- dev_data -> ats . qdep = pci_ats_queue_depth (pdev );
1859+ dev_data -> ats_enabled = 1 ;
1860+ dev_data -> ats_qdep = pci_ats_queue_depth (pdev );
18611861 dev_data -> pri_tlp = pci_prg_resp_pasid_required (pdev );
18621862 }
18631863 } else if (amd_iommu_iotlb_sup &&
18641864 pci_enable_ats (pdev , PAGE_SHIFT ) == 0 ) {
1865- dev_data -> ats . enabled = true ;
1866- dev_data -> ats . qdep = pci_ats_queue_depth (pdev );
1865+ dev_data -> ats_enabled = 1 ;
1866+ dev_data -> ats_qdep = pci_ats_queue_depth (pdev );
18671867 }
18681868
18691869skip_ats_check :
@@ -1920,10 +1920,10 @@ static void detach_device(struct device *dev)
19201920
19211921 if (domain -> flags & PD_IOMMUV2_MASK && dev_data -> iommu_v2 )
19221922 pdev_iommuv2_disable (to_pci_dev (dev ));
1923- else if (dev_data -> ats . enabled )
1923+ else if (dev_data -> ats_enabled )
19241924 pci_disable_ats (to_pci_dev (dev ));
19251925
1926- dev_data -> ats . enabled = false ;
1926+ dev_data -> ats_enabled = 0 ;
19271927
19281928out :
19291929 spin_unlock (& dev_data -> lock );
@@ -2013,7 +2013,7 @@ static void update_device_table(struct protection_domain *domain)
20132013 if (!iommu )
20142014 continue ;
20152015 set_dte_entry (iommu , dev_data -> devid , domain ,
2016- dev_data -> ats . enabled , dev_data -> iommu_v2 );
2016+ dev_data -> ats_enabled , dev_data -> iommu_v2 );
20172017 clone_aliases (iommu , dev_data -> dev );
20182018 }
20192019}
@@ -2612,10 +2612,10 @@ static int __flush_pasid(struct protection_domain *domain, u32 pasid,
26122612 There might be non-IOMMUv2 capable devices in an IOMMUv2
26132613 * domain.
26142614 */
2615- if (!dev_data -> ats . enabled )
2615+ if (!dev_data -> ats_enabled )
26162616 continue ;
26172617
2618- qdep = dev_data -> ats . qdep ;
2618+ qdep = dev_data -> ats_qdep ;
26192619 iommu = rlookup_amd_iommu (dev_data -> dev );
26202620 if (!iommu )
26212621 continue ;
0 commit comments