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torvaldstorvalds
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Merge tag 'drm-fixes-2023-03-10' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie: "Weekly fixes. msm and amdgpu are the vast majority of these, otherwise some straggler misc from last week for nouveau and cirrus and a mailmap update for a drm developer. mailmap: - add an entry nouveau: - fix system shutdown regression - build warning fix cirrus: - NULL ptr deref fix msm: - fix invalid ptr free in syncobj cleanup - sync GMU removal in teardown - a5xx preemption fixes - fix runpm imbalance - DPU hw fixes - stack corruption fix - clear DSPP reservation amdgpu: - Misc display fixes - UMC 8.10 fixes - Driver unload fixes - NBIO 7.3.0 fix - Error checking fixes for soc15, nv, soc21 read register interface - Fix video cap query for VCN 4.0.4 amdkfd: - Fix return check in doorbell handling" * tag 'drm-fixes-2023-03-10' of git://anongit.freedesktop.org/drm/drm: (42 commits) drm/amdgpu/soc21: Add video cap query support for VCN_4_0_4 drm/amdgpu: fix error checking in amdgpu_read_mm_registers for nv drm/amdgpu: fix error checking in amdgpu_read_mm_registers for soc21 drm/amdgpu: fix error checking in amdgpu_read_mm_registers for soc15 drm/amdgpu: Fix the warning info when removing amdgpu device drm/amdgpu: fix return value check in kfd drm/amd: Fix initialization mistake for NBIO 7.3.0 drm/amdgpu: Fix call trace warning and hang when removing amdgpu device mailmap: add mailmap entries for Faith. drm/msm: DEVFREQ_GOV_SIMPLE_ONDEMAND is no longer needed drm/amd/display: Update clock table to include highest clock setting drm/amd/pm: Enable ecc_info table support for smu v13_0_10 drm/amdgpu: Support umc node harvest config on umc v8_10 drm/connector: print max_requested_bpc in state debugfs drm/display: Don't block HDR_OUTPUT_METADATA on unknown EOTF drm/msm/dpu: clear DSPP reservations in rm release drm/msm/disp/dpu: fix sc7280_pp base offset drm/msm/dpu: fix stack smashing in dpu_hw_ctl_setup_blendstage drm/msm/dpu: don't use DPU_CLK_CTRL_CURSORn for DMA SSPP clocks drm/msm/dpu: fix clocks settings for msm8998 SSPP blocks ...
2 parents 388a810 + 519b233 commit b0d14d2

37 files changed

Lines changed: 280 additions & 191 deletions

‎.mailmap‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -136,6 +136,9 @@ Erik Kaneda <erik.kaneda@intel.com> <erik.schmauss@intel.com>
136136
Eugen Hristev <eugen.hristev@collabora.com> <eugen.hristev@microchip.com>
137137
Evgeniy Polyakov <johnpol@2ka.mipt.ru>
138138
Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> <ezequiel@collabora.com>
139+
Faith Ekstrand <faith.ekstrand@collabora.com> <jason@jlekstrand.net>
140+
Faith Ekstrand <faith.ekstrand@collabora.com> <jason.ekstrand@intel.com>
141+
Faith Ekstrand <faith.ekstrand@collabora.com> <jason.ekstrand@collabora.com>
139142
Felipe W Damasio <felipewd@terra.com.br>
140143
Felix Kuhling <fxkuehl@gmx.de>
141144
Felix Moeller <felix@derklecks.de>

‎drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c‎

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -543,6 +543,7 @@ static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev,
543543
struct harvest_table *harvest_info;
544544
u16 offset;
545545
int i;
546+
uint32_t umc_harvest_config = 0;
546547

547548
bhdr = (struct binary_header *)adev->mman.discovery_bin;
548549
offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset);
@@ -570,12 +571,17 @@ static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev,
570571
adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
571572
break;
572573
case UMC_HWID:
574+
umc_harvest_config |=
575+
1 << (le16_to_cpu(harvest_info->list[i].number_instance));
573576
(*umc_harvest_count)++;
574577
break;
575578
default:
576579
break;
577580
}
578581
}
582+
583+
adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) &
584+
~umc_harvest_config;
579585
}
580586

581587
/* ================================================== */
@@ -1156,8 +1162,10 @@ static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
11561162
AMDGPU_MAX_SDMA_INSTANCES);
11571163
}
11581164

1159-
if (le16_to_cpu(ip->hw_id) == UMC_HWID)
1165+
if (le16_to_cpu(ip->hw_id) == UMC_HWID) {
11601166
adev->gmc.num_umc++;
1167+
adev->umc.node_inst_num++;
1168+
}
11611169

11621170
for (k = 0; k < num_base_address; k++) {
11631171
/*

‎drivers/gpu/drm/amd/amdgpu/amdgpu_object.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1315,7 +1315,7 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)
13151315

13161316
if (!bo->resource || bo->resource->mem_type != TTM_PL_VRAM ||
13171317
!(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE) ||
1318-
adev->in_suspend || adev->shutdown)
1318+
adev->in_suspend || drm_dev_is_unplugged(adev_to_drm(adev)))
13191319
return;
13201320

13211321
if (WARN_ON_ONCE(!dma_resv_trylock(bo->base.resv)))

‎drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c‎

Lines changed: 1 addition & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -602,27 +602,14 @@ psp_cmd_submit_buf(struct psp_context *psp,
602602
struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
603603
{
604604
int ret;
605-
int index, idx;
605+
int index;
606606
int timeout = 20000;
607607
bool ras_intr = false;
608608
bool skip_unsupport = false;
609-
bool dev_entered;
610609

611610
if (psp->adev->no_hw_access)
612611
return 0;
613612

614-
dev_entered = drm_dev_enter(adev_to_drm(psp->adev), &idx);
615-
/*
616-
* We allow sending PSP messages LOAD_ASD and UNLOAD_TA without acquiring
617-
* a lock in drm_dev_enter during driver unload because we must call
618-
* drm_dev_unplug as the beginning of unload driver sequence . It is very
619-
* crucial that userspace can't access device instances anymore.
620-
*/
621-
if (!dev_entered)
622-
WARN_ON(psp->cmd_buf_mem->cmd_id != GFX_CMD_ID_LOAD_ASD &&
623-
psp->cmd_buf_mem->cmd_id != GFX_CMD_ID_UNLOAD_TA &&
624-
psp->cmd_buf_mem->cmd_id != GFX_CMD_ID_INVOKE_CMD);
625-
626613
memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
627614

628615
memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
@@ -686,8 +673,6 @@ psp_cmd_submit_buf(struct psp_context *psp,
686673
}
687674

688675
exit:
689-
if (dev_entered)
690-
drm_dev_exit(idx);
691676
return ret;
692677
}
693678

‎drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@
4242
#define LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) LOOP_UMC_INST((umc_inst)) LOOP_UMC_CH_INST((ch_inst))
4343

4444
#define LOOP_UMC_NODE_INST(node_inst) \
45-
for ((node_inst) = 0; (node_inst) < adev->umc.node_inst_num; (node_inst)++)
45+
for_each_set_bit((node_inst), &(adev->umc.active_mask), adev->umc.node_inst_num)
4646

4747
#define LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) \
4848
LOOP_UMC_NODE_INST((node_inst)) LOOP_UMC_INST_AND_CH((umc_inst), (ch_inst))
@@ -69,7 +69,7 @@ struct amdgpu_umc {
6969
/* number of umc instance with memory map register access */
7070
uint32_t umc_inst_num;
7171

72-
/*number of umc node instance with memory map register access*/
72+
/* Total number of umc node instance including harvest one */
7373
uint32_t node_inst_num;
7474

7575
/* UMC regiser per channel offset */
@@ -82,6 +82,9 @@ struct amdgpu_umc {
8282

8383
const struct amdgpu_umc_funcs *funcs;
8484
struct amdgpu_umc_ras *ras;
85+
86+
/* active mask for umc node instance */
87+
unsigned long active_mask;
8588
};
8689

8790
int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);

‎drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -567,7 +567,6 @@ static void gmc_v11_0_set_umc_funcs(struct amdgpu_device *adev)
567567
case IP_VERSION(8, 10, 0):
568568
adev->umc.channel_inst_num = UMC_V8_10_CHANNEL_INSTANCE_NUM;
569569
adev->umc.umc_inst_num = UMC_V8_10_UMC_INSTANCE_NUM;
570-
adev->umc.node_inst_num = adev->gmc.num_umc;
571570
adev->umc.max_ras_err_cnt_per_query = UMC_V8_10_TOTAL_CHANNEL_NUM(adev);
572571
adev->umc.channel_offs = UMC_V8_10_PER_CHANNEL_OFFSET;
573572
adev->umc.retire_unit = UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM;

‎drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c‎

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -382,11 +382,6 @@ static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
382382
if (def != data)
383383
WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3), data);
384384
break;
385-
case IP_VERSION(7, 5, 1):
386-
data = RREG32_SOC15(NBIO, 0, regRCC_DEV2_EPF0_STRAP2);
387-
data &= ~RCC_DEV2_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV2_F0_MASK;
388-
WREG32_SOC15(NBIO, 0, regRCC_DEV2_EPF0_STRAP2, data);
389-
fallthrough;
390385
default:
391386
def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL));
392387
data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL,
@@ -399,6 +394,15 @@ static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
399394
break;
400395
}
401396

397+
switch (adev->ip_versions[NBIO_HWIP][0]) {
398+
case IP_VERSION(7, 3, 0):
399+
case IP_VERSION(7, 5, 1):
400+
data = RREG32_SOC15(NBIO, 0, regRCC_DEV2_EPF0_STRAP2);
401+
data &= ~RCC_DEV2_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV2_F0_MASK;
402+
WREG32_SOC15(NBIO, 0, regRCC_DEV2_EPF0_STRAP2, data);
403+
break;
404+
}
405+
402406
if (amdgpu_sriov_vf(adev))
403407
adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
404408
regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;

‎drivers/gpu/drm/amd/amdgpu/nv.c‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -444,9 +444,10 @@ static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
444444
*value = 0;
445445
for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
446446
en = &nv_allowed_read_registers[i];
447-
if (adev->reg_offset[en->hwip][en->inst] &&
448-
reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
449-
+ en->reg_offset))
447+
if (!adev->reg_offset[en->hwip][en->inst])
448+
continue;
449+
else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
450+
+ en->reg_offset))
450451
continue;
451452

452453
*value = nv_get_register_value(adev,

‎drivers/gpu/drm/amd/amdgpu/soc15.c‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -439,8 +439,9 @@ static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
439439
*value = 0;
440440
for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
441441
en = &soc15_allowed_read_registers[i];
442-
if (adev->reg_offset[en->hwip][en->inst] &&
443-
reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
442+
if (!adev->reg_offset[en->hwip][en->inst])
443+
continue;
444+
else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
444445
+ en->reg_offset))
445446
continue;
446447

‎drivers/gpu/drm/amd/amdgpu/soc21.c‎

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -111,6 +111,7 @@ static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode,
111111
switch (adev->ip_versions[UVD_HWIP][0]) {
112112
case IP_VERSION(4, 0, 0):
113113
case IP_VERSION(4, 0, 2):
114+
case IP_VERSION(4, 0, 4):
114115
if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {
115116
if (encode)
116117
*codecs = &vcn_4_0_0_video_codecs_encode_vcn1;
@@ -291,9 +292,10 @@ static int soc21_read_register(struct amdgpu_device *adev, u32 se_num,
291292
*value = 0;
292293
for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) {
293294
en = &soc21_allowed_read_registers[i];
294-
if (adev->reg_offset[en->hwip][en->inst] &&
295-
reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
296-
+ en->reg_offset))
295+
if (!adev->reg_offset[en->hwip][en->inst])
296+
continue;
297+
else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
298+
+ en->reg_offset))
297299
continue;
298300

299301
*value = soc21_get_register_value(adev,

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