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pinctrl: samsung: Add Exynos7885 SoC specific data
Add Samsung Exynos7885 SoC specific data to enable pinctrl support for all platforms based on Exynos7885. Signed-off-by: David Virag <virag.david003@gmail.com> Link: https://lore.kernel.org/r/20211031231720.46994-1-virag.david003@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
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‎drivers/pinctrl/samsung/pinctrl-exynos-arm64.c‎

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@@ -441,6 +441,87 @@ const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = {
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.num_ctrl = ARRAY_SIZE(exynos7_pin_ctrl),
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};
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/* pin banks of exynos7885 pin-controller 0 (ALIVE) */
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static const struct samsung_pin_bank_data exynos7885_pin_banks0[] __initconst = {
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EXYNOS_PIN_BANK_EINTN(3, 0x000, "etc0"),
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EXYNOS_PIN_BANK_EINTN(3, 0x020, "etc1"),
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EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa0", 0x00),
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EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa1", 0x04),
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EXYNOS850_PIN_BANK_EINTW(8, 0x080, "gpa2", 0x08),
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EXYNOS850_PIN_BANK_EINTW(5, 0x0a0, "gpq0", 0x0c),
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};
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/* pin banks of exynos7885 pin-controller 1 (DISPAUD) */
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static const struct samsung_pin_bank_data exynos7885_pin_banks1[] __initconst = {
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EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
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EXYNOS850_PIN_BANK_EINTG(4, 0x020, "gpb1", 0x04),
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EXYNOS850_PIN_BANK_EINTG(5, 0x040, "gpb2", 0x08),
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};
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/* pin banks of exynos7885 pin-controller 2 (FSYS) */
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static const struct samsung_pin_bank_data exynos7885_pin_banks2[] __initconst = {
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EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00),
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EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf2", 0x04),
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EXYNOS850_PIN_BANK_EINTG(6, 0x040, "gpf3", 0x08),
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EXYNOS850_PIN_BANK_EINTG(6, 0x060, "gpf4", 0x0c),
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};
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/* pin banks of exynos7885 pin-controller 3 (TOP) */
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static const struct samsung_pin_bank_data exynos7885_pin_banks3[] __initconst = {
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EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpp0", 0x00),
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EXYNOS850_PIN_BANK_EINTG(3, 0x020, "gpg0", 0x04),
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EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp1", 0x08),
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EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp2", 0x0c),
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EXYNOS850_PIN_BANK_EINTG(3, 0x080, "gpp3", 0x10),
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EXYNOS850_PIN_BANK_EINTG(6, 0x0a0, "gpp4", 0x14),
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EXYNOS850_PIN_BANK_EINTG(4, 0x0c0, "gpp5", 0x18),
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EXYNOS850_PIN_BANK_EINTG(5, 0x0e0, "gpp6", 0x1c),
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EXYNOS850_PIN_BANK_EINTG(2, 0x100, "gpp7", 0x20),
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EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpp8", 0x24),
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EXYNOS850_PIN_BANK_EINTG(8, 0x140, "gpg1", 0x28),
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EXYNOS850_PIN_BANK_EINTG(8, 0x160, "gpg2", 0x2c),
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EXYNOS850_PIN_BANK_EINTG(8, 0x180, "gpg3", 0x30),
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EXYNOS850_PIN_BANK_EINTG(2, 0x1a0, "gpg4", 0x34),
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EXYNOS850_PIN_BANK_EINTG(4, 0x1c0, "gpc0", 0x38),
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EXYNOS850_PIN_BANK_EINTG(8, 0x1e0, "gpc1", 0x3c),
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EXYNOS850_PIN_BANK_EINTG(8, 0x200, "gpc2", 0x40),
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};
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const struct samsung_pin_ctrl exynos7885_pin_ctrl[] __initconst = {
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{
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/* pin-controller instance 0 Alive data */
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.pin_banks = exynos7885_pin_banks0,
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.nr_banks = ARRAY_SIZE(exynos7885_pin_banks0),
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.eint_gpio_init = exynos_eint_gpio_init,
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.eint_wkup_init = exynos_eint_wkup_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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}, {
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/* pin-controller instance 1 DISPAUD data */
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.pin_banks = exynos7885_pin_banks1,
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.nr_banks = ARRAY_SIZE(exynos7885_pin_banks1),
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}, {
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/* pin-controller instance 2 FSYS data */
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.pin_banks = exynos7885_pin_banks2,
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.nr_banks = ARRAY_SIZE(exynos7885_pin_banks2),
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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}, {
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/* pin-controller instance 3 TOP data */
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.pin_banks = exynos7885_pin_banks3,
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.nr_banks = ARRAY_SIZE(exynos7885_pin_banks3),
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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},
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};
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const struct samsung_pinctrl_of_match_data exynos7885_of_data __initconst = {
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.ctrl = exynos7885_pin_ctrl,
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.num_ctrl = ARRAY_SIZE(exynos7885_pin_ctrl),
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};
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/* pin banks of exynos850 pin-controller 0 (ALIVE) */
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static const struct samsung_pin_bank_data exynos850_pin_banks0[] __initconst = {
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/* Must start with EINTG banks, ordered by EINT group number. */

‎drivers/pinctrl/samsung/pinctrl-samsung.c‎

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@@ -1264,6 +1264,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
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.data = &exynos5433_of_data },
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{ .compatible = "samsung,exynos7-pinctrl",
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.data = &exynos7_of_data },
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{ .compatible = "samsung,exynos7885-pinctrl",
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.data = &exynos7885_of_data },
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{ .compatible = "samsung,exynos850-pinctrl",
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.data = &exynos850_of_data },
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{ .compatible = "samsung,exynosautov9-pinctrl",

‎drivers/pinctrl/samsung/pinctrl-samsung.h‎

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@@ -339,6 +339,7 @@ extern const struct samsung_pinctrl_of_match_data exynos5410_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos5420_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos5433_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos7_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
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extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data;
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extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data;

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