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Russell King (Oracle)kuba-moo
Russell King (Oracle)
authored and
kuba-moo
committed
net: stmmac: rk: rk3506, rk3528 and rk3588 have rmii_mode in clock register
rk3506, rk3528 and rk3588 have the rmii_mode bit in the clock GRF register rather than the gmac GRF register. Provide a mask for this field in the clock register, and convert these SoCs to use this. Add the necessary code in rk_gmac_powerup() to write this field. This allows us to get rid of these SoCs set_to_rmii() function. As such, we need to mark these SoCs as supporting RMII mode. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Heiko Stuebner <heiko@sntech.de> #px30,rk3328,rk3568,rk3588 Link: https://patch.msgid.link/E1vnYyB-00000007hpF-1dwK@rmk-PC.armlinux.org.uk Signed-off-by: Jakub Kicinski <kuba@kernel.org>
1 parent 5c1fc7c commit b10d56b

1 file changed

Lines changed: 24 additions & 40 deletions

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‎drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c‎

Lines changed: 24 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,7 @@ struct rk_clock_fields {
3838
u16 gmii_clk_sel_mask;
3939
u16 rmii_clk_sel_mask;
4040
u16 rmii_gate_en_mask;
41+
u16 rmii_mode_mask;
4142
u16 mac_speed_mask;
4243
};
4344

@@ -708,21 +709,15 @@ static int rk3506_init(struct rk_priv_data *bsp_priv)
708709
}
709710
}
710711

711-
static void rk3506_set_to_rmii(struct rk_priv_data *bsp_priv)
712-
{
713-
unsigned int id = bsp_priv->id, offset;
714-
715-
offset = (id == 1) ? RK3506_GRF_SOC_CON11 : RK3506_GRF_SOC_CON8;
716-
regmap_write(bsp_priv->grf, offset, RK3506_GMAC_RMII_MODE);
717-
}
718-
719712
static const struct rk_gmac_ops rk3506_ops = {
720713
.init = rk3506_init,
721-
.set_to_rmii = rk3506_set_to_rmii,
722714

723715
.clock.io_clksel_io_mask = BIT_U16(5),
724716
.clock.rmii_clk_sel_mask = BIT_U16(3),
725717
.clock.rmii_gate_en_mask = BIT_U16(2),
718+
.clock.rmii_mode_mask = BIT_U16(1),
719+
720+
.supports_rmii = true,
726721

727722
.regs_valid = true,
728723
.regs = {
@@ -746,17 +741,14 @@ static const struct rk_gmac_ops rk3506_ops = {
746741
#define RK3528_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(15, 8, val)
747742
#define RK3528_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(7, 0, val)
748743

749-
#define RK3528_GMAC0_PHY_INTF_SEL_RMII GRF_BIT(1)
750-
#define RK3528_GMAC1_PHY_INTF_SEL_RGMII GRF_CLR_BIT(8)
751-
#define RK3528_GMAC1_PHY_INTF_SEL_RMII GRF_BIT(8)
752-
753744
static int rk3528_init(struct rk_priv_data *bsp_priv)
754745
{
755746
switch (bsp_priv->id) {
756747
case 0:
757748
bsp_priv->clock_grf_reg = RK3528_VO_GRF_GMAC_CON;
758749
bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(3);
759750
bsp_priv->clock.rmii_gate_en_mask = BIT_U16(2);
751+
bsp_priv->clock.rmii_mode_mask = BIT_U16(1);
760752
bsp_priv->supports_rgmii = false;
761753
return 0;
762754

@@ -766,6 +758,7 @@ static int rk3528_init(struct rk_priv_data *bsp_priv)
766758
bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(11, 10);
767759
bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(10);
768760
bsp_priv->clock.rmii_gate_en_mask = BIT_U16(9);
761+
bsp_priv->clock.rmii_mode_mask = BIT_U16(8);
769762
return 0;
770763

771764
default:
@@ -776,9 +769,6 @@ static int rk3528_init(struct rk_priv_data *bsp_priv)
776769
static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv,
777770
int tx_delay, int rx_delay)
778771
{
779-
regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
780-
RK3528_GMAC1_PHY_INTF_SEL_RGMII);
781-
782772
regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
783773
DELAY_ENABLE(RK3528, tx_delay, rx_delay));
784774

@@ -787,16 +777,6 @@ static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv,
787777
RK3528_GMAC_CLK_TX_DL_CFG(tx_delay));
788778
}
789779

790-
static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv)
791-
{
792-
if (bsp_priv->id == 1)
793-
regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
794-
RK3528_GMAC1_PHY_INTF_SEL_RMII);
795-
else
796-
regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON,
797-
RK3528_GMAC0_PHY_INTF_SEL_RMII);
798-
}
799-
800780
static void rk3528_integrated_phy_powerup(struct rk_priv_data *bsp_priv)
801781
{
802782
rk_gmac_integrated_fephy_powerup(bsp_priv, RK3528_VO_GRF_MACPHY_CON0);
@@ -810,9 +790,11 @@ static void rk3528_integrated_phy_powerdown(struct rk_priv_data *bsp_priv)
810790
static const struct rk_gmac_ops rk3528_ops = {
811791
.init = rk3528_init,
812792
.set_to_rgmii = rk3528_set_to_rgmii,
813-
.set_to_rmii = rk3528_set_to_rmii,
814793
.integrated_phy_powerup = rk3528_integrated_phy_powerup,
815794
.integrated_phy_powerdown = rk3528_integrated_phy_powerdown,
795+
796+
.supports_rmii = true,
797+
816798
.regs_valid = true,
817799
.regs = {
818800
0xffbd0000, /* gmac0 */
@@ -988,9 +970,6 @@ static const struct rk_gmac_ops rk3576_ops = {
988970
#define RK3588_GRF_GMAC_CON0 0X0008
989971
#define RK3588_GRF_CLK_CON1 0X0070
990972

991-
#define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id))
992-
#define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id))
993-
994973
static int rk3588_init(struct rk_priv_data *bsp_priv)
995974
{
996975
switch (bsp_priv->id) {
@@ -1000,6 +979,7 @@ static int rk3588_init(struct rk_priv_data *bsp_priv)
1000979
bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(3, 2);
1001980
bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(2);
1002981
bsp_priv->clock.rmii_gate_en_mask = BIT_U16(1);
982+
bsp_priv->clock.rmii_mode_mask = BIT_U16(0);
1003983
return 0;
1004984

1005985
case 1:
@@ -1008,6 +988,7 @@ static int rk3588_init(struct rk_priv_data *bsp_priv)
1008988
bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(8, 7);
1009989
bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(7);
1010990
bsp_priv->clock.rmii_gate_en_mask = BIT_U16(6);
991+
bsp_priv->clock.rmii_mode_mask = BIT_U16(5);
1011992
return 0;
1012993

1013994
default:
@@ -1023,9 +1004,6 @@ static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv,
10231004
offset_con = bsp_priv->id == 1 ? RK3588_GRF_GMAC_CON9 :
10241005
RK3588_GRF_GMAC_CON8;
10251006

1026-
regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
1027-
RK3588_GMAC_CLK_RGMII_MODE(id));
1028-
10291007
regmap_write(bsp_priv->grf, RK3588_GRF_GMAC_CON7,
10301008
RK3588_GMAC_RXCLK_DLY_ENABLE(id) |
10311009
RK3588_GMAC_TXCLK_DLY_ENABLE(id));
@@ -1035,23 +1013,18 @@ static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv,
10351013
RK3588_GMAC_CLK_TX_DL_CFG(tx_delay));
10361014
}
10371015

1038-
static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv)
1039-
{
1040-
regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
1041-
RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id));
1042-
}
1043-
10441016
static const struct rk_gmac_ops rk3588_ops = {
10451017
.init = rk3588_init,
10461018
.set_to_rgmii = rk3588_set_to_rgmii,
1047-
.set_to_rmii = rk3588_set_to_rmii,
10481019

10491020
.gmac_grf_reg_in_php = true,
10501021
.gmac_grf_reg = RK3588_GRF_GMAC_CON0,
10511022

10521023
.clock_grf_reg_in_php = true,
10531024
.clock_grf_reg = RK3588_GRF_CLK_CON1,
10541025

1026+
.supports_rmii = true,
1027+
10551028
.php_grf_required = true,
10561029
.regs_valid = true,
10571030
.regs = {
@@ -1432,6 +1405,17 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
14321405
}
14331406
}
14341407

1408+
if (bsp_priv->clock.rmii_mode_mask) {
1409+
val = rk_encode_wm16(intf == PHY_INTF_SEL_RMII,
1410+
bsp_priv->clock.rmii_mode_mask);
1411+
1412+
ret = rk_write_clock_grf_reg(bsp_priv, val);
1413+
if (ret < 0) {
1414+
gmac_clk_enable(bsp_priv, false);
1415+
return ret;
1416+
}
1417+
}
1418+
14351419
/*rmii or rgmii*/
14361420
switch (bsp_priv->phy_iface) {
14371421
case PHY_INTERFACE_MODE_RGMII:

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