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pinctrl: ocelot: Extend support for lan9645xf family
Extend pinctrl-ocelot driver to support the lan9645xf chip family. Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com> Reviewed-by: Daniel Machon <daniel.machon@microchip.com> Signed-off-by: Jens Emil Schulz Østergaard <jensemil.schulzostergaard@microchip.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
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‎drivers/pinctrl/pinctrl-ocelot.c‎

Lines changed: 177 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -97,6 +97,8 @@ enum {
9797
FUNC_FC_SHRD20,
9898
FUNC_FUSA,
9999
FUNC_GPIO,
100+
FUNC_I2C,
101+
FUNC_I2C_Sa,
100102
FUNC_IB_TRG_a,
101103
FUNC_IB_TRG_b,
102104
FUNC_IB_TRG_c,
@@ -112,9 +114,11 @@ enum {
112114
FUNC_IRQ1,
113115
FUNC_IRQ1_IN,
114116
FUNC_IRQ1_OUT,
117+
FUNC_IRQ2,
115118
FUNC_IRQ3,
116119
FUNC_IRQ4,
117120
FUNC_EXT_IRQ,
121+
FUNC_MACLED,
118122
FUNC_MIIM,
119123
FUNC_MIIM_a,
120124
FUNC_MIIM_b,
@@ -126,6 +130,7 @@ enum {
126130
FUNC_OB_TRG_a,
127131
FUNC_OB_TRG_b,
128132
FUNC_PHY_LED,
133+
FUNC_PHY_DBG,
129134
FUNC_PCI_WAKE,
130135
FUNC_MD,
131136
FUNC_PCIE_PERST,
@@ -156,10 +161,12 @@ enum {
156161
FUNC_SG0,
157162
FUNC_SG1,
158163
FUNC_SG2,
164+
FUNC_SPI,
159165
FUNC_SGPIO_a,
160166
FUNC_SGPIO_b,
161167
FUNC_SI,
162168
FUNC_SI2,
169+
FUNC_SI_Sa,
163170
FUNC_SYNCE,
164171
FUNC_TACHO,
165172
FUNC_TACHO_a,
@@ -188,6 +195,7 @@ enum {
188195
FUNC_EMMC_SD,
189196
FUNC_REF_CLK,
190197
FUNC_RCVRD_CLK,
198+
FUNC_RGMII,
191199
FUNC_MAX
192200
};
193201

@@ -237,6 +245,8 @@ static const char *const ocelot_function_names[] = {
237245
[FUNC_FC_SHRD20] = "fc_shrd20",
238246
[FUNC_FUSA] = "fusa",
239247
[FUNC_GPIO] = "gpio",
248+
[FUNC_I2C] = "i2c",
249+
[FUNC_I2C_Sa] = "i2c_slave_a",
240250
[FUNC_IB_TRG_a] = "ib_trig_a",
241251
[FUNC_IB_TRG_b] = "ib_trig_b",
242252
[FUNC_IB_TRG_c] = "ib_trig_c",
@@ -252,9 +262,11 @@ static const char *const ocelot_function_names[] = {
252262
[FUNC_IRQ1] = "irq1",
253263
[FUNC_IRQ1_IN] = "irq1_in",
254264
[FUNC_IRQ1_OUT] = "irq1_out",
265+
[FUNC_IRQ2] = "irq2",
255266
[FUNC_IRQ3] = "irq3",
256267
[FUNC_IRQ4] = "irq4",
257268
[FUNC_EXT_IRQ] = "ext_irq",
269+
[FUNC_MACLED] = "mac_led",
258270
[FUNC_MIIM] = "miim",
259271
[FUNC_MIIM_a] = "miim_a",
260272
[FUNC_MIIM_b] = "miim_b",
@@ -263,6 +275,7 @@ static const char *const ocelot_function_names[] = {
263275
[FUNC_MIIM_Sb] = "miim_slave_b",
264276
[FUNC_MIIM_IRQ] = "miim_irq",
265277
[FUNC_PHY_LED] = "phy_led",
278+
[FUNC_PHY_DBG] = "phy_dbg",
266279
[FUNC_PCI_WAKE] = "pci_wake",
267280
[FUNC_PCIE_PERST] = "pcie_perst",
268281
[FUNC_MD] = "md",
@@ -300,6 +313,8 @@ static const char *const ocelot_function_names[] = {
300313
[FUNC_SGPIO_b] = "sgpio_b",
301314
[FUNC_SI] = "si",
302315
[FUNC_SI2] = "si2",
316+
[FUNC_SI_Sa] = "si_slave_a",
317+
[FUNC_SPI] = "spi",
303318
[FUNC_SYNCE] = "synce",
304319
[FUNC_TACHO] = "tacho",
305320
[FUNC_TACHO_a] = "tacho_a",
@@ -328,6 +343,7 @@ static const char *const ocelot_function_names[] = {
328343
[FUNC_EMMC_SD] = "emmc_sd",
329344
[FUNC_REF_CLK] = "ref_clk",
330345
[FUNC_RCVRD_CLK] = "rcvrd_clk",
346+
[FUNC_RGMII] = "rgmii",
331347
};
332348

333349
struct ocelot_pmx_func {
@@ -1323,6 +1339,132 @@ static const struct pinctrl_pin_desc lan969x_pins[] = {
13231339
LAN969X_PIN(66),
13241340
};
13251341

1342+
#define LAN9645X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \
1343+
static struct ocelot_pin_caps lan9645x_pin_##p = { \
1344+
.pin = p, \
1345+
.functions = { \
1346+
FUNC_##f0, FUNC_##f1, FUNC_##f2, \
1347+
FUNC_##f3 \
1348+
}, \
1349+
.a_functions = { \
1350+
FUNC_##f4, FUNC_##f5, FUNC_##f6, \
1351+
FUNC_##f7 \
1352+
}, \
1353+
}
1354+
1355+
/* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */
1356+
LAN9645X_P(0, GPIO, SPI, SI_Sa, I2C_Sa, MIIM_Sa, UART, MIIM, PHY_DBG);
1357+
LAN9645X_P(1, GPIO, SPI, SI_Sa, I2C_Sa, MIIM_Sa, UART, MIIM, PHY_DBG);
1358+
LAN9645X_P(2, GPIO, SPI, SI_Sa, I2C, NONE, NONE, NONE, PHY_DBG);
1359+
LAN9645X_P(3, GPIO, SPI, SI_Sa, I2C, MIIM_Sa, NONE, NONE, PHY_DBG);
1360+
LAN9645X_P(4, GPIO, RGMII, TWI_SCL_M, I2C, NONE, NONE, SI_Sa, PHY_DBG);
1361+
LAN9645X_P(5, GPIO, RGMII, TWI_SCL_M, I2C, NONE, NONE, SI_Sa, PHY_DBG);
1362+
LAN9645X_P(6, GPIO, RGMII, TWI_SCL_M, NONE, NONE, NONE, SI_Sa, PHY_DBG);
1363+
LAN9645X_P(7, GPIO, RGMII, TWI_SCL_M, SFP, SGPIO_a, MIIM, SI_Sa, PHY_DBG);
1364+
LAN9645X_P(8, GPIO, RGMII, TWI_SCL_M, SFP, SGPIO_a, MIIM, NONE, PHY_DBG);
1365+
LAN9645X_P(9, GPIO, RGMII, TWI_SCL_M, RECO_CLK, SGPIO_a, IRQ1, UART, PHY_DBG);
1366+
LAN9645X_P(10, GPIO, RGMII, TWI_SCL_M, RECO_CLK, SGPIO_a, IRQ2, UART, PHY_DBG);
1367+
LAN9645X_P(11, GPIO, RGMII, TWI_SCL_M, MIIM, NONE, IRQ3, NONE, PHY_DBG);
1368+
LAN9645X_P(12, GPIO, RGMII, TWI_SCL_M, MIIM, PTP0, NONE, NONE, PHY_DBG);
1369+
LAN9645X_P(13, GPIO, RGMII, TWI_SCL_M, CLKMON, PTP1, MACLED, NONE, PHY_DBG);
1370+
LAN9645X_P(14, GPIO, RGMII, TWI_SCL_M, CLKMON, PTP2, MACLED, NONE, PHY_DBG);
1371+
LAN9645X_P(15, GPIO, RGMII, TWI_SCL_M, CLKMON, PTP3, NONE, NONE, PHY_DBG);
1372+
LAN9645X_P(16, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG);
1373+
LAN9645X_P(17, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG);
1374+
LAN9645X_P(18, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG);
1375+
LAN9645X_P(19, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG);
1376+
LAN9645X_P(20, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG);
1377+
LAN9645X_P(21, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG);
1378+
LAN9645X_P(22, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG);
1379+
LAN9645X_P(23, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG);
1380+
LAN9645X_P(24, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG);
1381+
LAN9645X_P(25, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG);
1382+
LAN9645X_P(26, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG);
1383+
LAN9645X_P(27, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG);
1384+
LAN9645X_P(28, GPIO, RECO_CLK, MIIM, NONE, NONE, NONE, NONE, R);
1385+
LAN9645X_P(29, GPIO, RECO_CLK, MIIM, NONE, NONE, NONE, NONE, R);
1386+
LAN9645X_P(30, GPIO, PTP0, I2C, UART, NONE, NONE, NONE, R);
1387+
LAN9645X_P(31, GPIO, PTP1, TWI_SCL_M, UART, NONE, NONE, NONE, R);
1388+
LAN9645X_P(32, GPIO, PTP2, TWI_SCL_M, NONE, NONE, NONE, NONE, R);
1389+
LAN9645X_P(33, GPIO, PTP3, IRQ0, NONE, NONE, NONE, NONE, R);
1390+
LAN9645X_P(34, GPIO, RECO_CLK, PHY_LED, PHY_LED, NONE, NONE, NONE, R);
1391+
LAN9645X_P(35, GPIO, RECO_CLK, PHY_LED, PHY_LED, NONE, MACLED, NONE, R);
1392+
LAN9645X_P(36, GPIO, PTP0, PHY_LED, PHY_LED, NONE, MACLED, NONE, R);
1393+
LAN9645X_P(37, GPIO, PTP1, PHY_LED, PHY_LED, NONE, MACLED, NONE, R);
1394+
LAN9645X_P(38, GPIO, NONE, PHY_LED, PHY_LED, NONE, MACLED, NONE, R);
1395+
LAN9645X_P(39, GPIO, UART, PHY_LED, NONE, NONE, MACLED, NONE, R);
1396+
LAN9645X_P(40, GPIO, SPI, PHY_LED, SGPIO_a, NONE, MACLED, NONE, R);
1397+
LAN9645X_P(41, GPIO, SPI, PHY_LED, SGPIO_a, IRQ1, MACLED, NONE, R);
1398+
LAN9645X_P(42, GPIO, SPI, PHY_LED, SGPIO_a, IRQ2, MACLED, SFP, R);
1399+
LAN9645X_P(43, GPIO, SPI, PHY_LED, SGPIO_a, IRQ3, MACLED, SFP, R);
1400+
LAN9645X_P(44, GPIO, MIIM, I2C, NONE, NONE, NONE, NONE, R);
1401+
LAN9645X_P(45, GPIO, MIIM, I2C, NONE, NONE, NONE, NONE, R);
1402+
LAN9645X_P(46, GPIO, NONE, PHY_LED, NONE, NONE, NONE, NONE, R);
1403+
LAN9645X_P(47, GPIO, NONE, PHY_LED, NONE, NONE, NONE, NONE, R);
1404+
LAN9645X_P(48, GPIO, MIIM_Sa, PHY_LED, NONE, NONE, NONE, NONE, R);
1405+
LAN9645X_P(49, GPIO, MIIM_Sa, PHY_LED, I2C_Sa, NONE, NONE, NONE, R);
1406+
LAN9645X_P(50, GPIO, MIIM_Sa, PHY_LED, I2C_Sa, NONE, NONE, NONE, R);
1407+
1408+
#define LAN9645X_PIN(n) { \
1409+
.number = n, \
1410+
.name = "GPIO_"#n, \
1411+
.drv_data = &lan9645x_pin_##n \
1412+
}
1413+
1414+
static const struct pinctrl_pin_desc lan9645x_pins[] = {
1415+
LAN9645X_PIN(0),
1416+
LAN9645X_PIN(1),
1417+
LAN9645X_PIN(2),
1418+
LAN9645X_PIN(3),
1419+
LAN9645X_PIN(4),
1420+
LAN9645X_PIN(5),
1421+
LAN9645X_PIN(6),
1422+
LAN9645X_PIN(7),
1423+
LAN9645X_PIN(8),
1424+
LAN9645X_PIN(9),
1425+
LAN9645X_PIN(10),
1426+
LAN9645X_PIN(11),
1427+
LAN9645X_PIN(12),
1428+
LAN9645X_PIN(13),
1429+
LAN9645X_PIN(14),
1430+
LAN9645X_PIN(15),
1431+
LAN9645X_PIN(16),
1432+
LAN9645X_PIN(17),
1433+
LAN9645X_PIN(18),
1434+
LAN9645X_PIN(19),
1435+
LAN9645X_PIN(20),
1436+
LAN9645X_PIN(21),
1437+
LAN9645X_PIN(22),
1438+
LAN9645X_PIN(23),
1439+
LAN9645X_PIN(24),
1440+
LAN9645X_PIN(25),
1441+
LAN9645X_PIN(26),
1442+
LAN9645X_PIN(27),
1443+
LAN9645X_PIN(28),
1444+
LAN9645X_PIN(29),
1445+
LAN9645X_PIN(30),
1446+
LAN9645X_PIN(31),
1447+
LAN9645X_PIN(32),
1448+
LAN9645X_PIN(33),
1449+
LAN9645X_PIN(34),
1450+
LAN9645X_PIN(35),
1451+
LAN9645X_PIN(36),
1452+
LAN9645X_PIN(37),
1453+
LAN9645X_PIN(38),
1454+
LAN9645X_PIN(39),
1455+
LAN9645X_PIN(40),
1456+
LAN9645X_PIN(41),
1457+
LAN9645X_PIN(42),
1458+
LAN9645X_PIN(43),
1459+
LAN9645X_PIN(44),
1460+
LAN9645X_PIN(45),
1461+
LAN9645X_PIN(46),
1462+
LAN9645X_PIN(47),
1463+
LAN9645X_PIN(48),
1464+
LAN9645X_PIN(49),
1465+
LAN9645X_PIN(50),
1466+
};
1467+
13261468
static int ocelot_get_functions_count(struct pinctrl_dev *pctldev)
13271469
{
13281470
return ARRAY_SIZE(ocelot_function_names);
@@ -1471,6 +1613,13 @@ static int lan966x_gpio_request_enable(struct pinctrl_dev *pctldev,
14711613
return 0;
14721614
}
14731615

1616+
static int lan9645x_gpio_request_enable(struct pinctrl_dev *pctldev,
1617+
struct pinctrl_gpio_range *range,
1618+
unsigned int offset)
1619+
{
1620+
return 0;
1621+
}
1622+
14741623
static const struct pinmux_ops ocelot_pmx_ops = {
14751624
.get_functions_count = ocelot_get_functions_count,
14761625
.get_function_name = ocelot_get_function_name,
@@ -1489,6 +1638,15 @@ static const struct pinmux_ops lan966x_pmx_ops = {
14891638
.gpio_request_enable = lan966x_gpio_request_enable,
14901639
};
14911640

1641+
static const struct pinmux_ops lan9645x_pmx_ops = {
1642+
.get_functions_count = ocelot_get_functions_count,
1643+
.get_function_name = ocelot_get_function_name,
1644+
.get_function_groups = ocelot_get_function_groups,
1645+
.set_mux = lan966x_pinmux_set_mux,
1646+
.gpio_set_direction = ocelot_gpio_set_direction,
1647+
.gpio_request_enable = lan9645x_gpio_request_enable,
1648+
};
1649+
14921650
static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev)
14931651
{
14941652
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
@@ -1886,6 +2044,24 @@ static const struct ocelot_match_data lan969x_desc = {
18862044
},
18872045
};
18882046

2047+
static struct ocelot_match_data lan9645xf_desc = {
2048+
.desc = {
2049+
.name = "lan9645xf-pinctrl",
2050+
.pins = lan9645x_pins,
2051+
.npins = ARRAY_SIZE(lan9645x_pins),
2052+
.pctlops = &ocelot_pctl_ops,
2053+
.pmxops = &lan9645x_pmx_ops,
2054+
.confops = &ocelot_confops,
2055+
.owner = THIS_MODULE,
2056+
},
2057+
.pincfg_data = {
2058+
.pd_bit = BIT(3),
2059+
.pu_bit = BIT(2),
2060+
.drive_bits = GENMASK(1, 0),
2061+
},
2062+
.n_alt_modes = 7,
2063+
};
2064+
18892065
static int ocelot_create_group_func_map(struct device *dev,
18902066
struct ocelot_pinctrl *info)
18912067
{
@@ -2220,6 +2396,7 @@ static const struct of_device_id ocelot_pinctrl_of_match[] = {
22202396
{ .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc },
22212397
{ .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc },
22222398
{ .compatible = "microchip,lan9691-pinctrl", .data = &lan969x_desc },
2399+
{ .compatible = "microchip,lan96455f-pinctrl", .data = &lan9645xf_desc },
22232400
{},
22242401
};
22252402
MODULE_DEVICE_TABLE(of, ocelot_pinctrl_of_match);

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