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Ansuelandersson
Ansuel
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andersson
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clk: qcom: gcc-ipq806x: add CryptoEngine clocks
Add missing CryptoEngine clocks and pll11 required clock. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Tested-by: Jonathan McDowell <noodles@earth.li> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220226135235.10051-13-ansuelsmth@gmail.com
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‎drivers/clk/qcom/gcc-ipq806x.c‎

Lines changed: 244 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -256,6 +256,24 @@ static struct clk_pll pll18 = {
256256
},
257257
};
258258

259+
static struct clk_pll pll11 = {
260+
.l_reg = 0x3184,
261+
.m_reg = 0x3188,
262+
.n_reg = 0x318c,
263+
.config_reg = 0x3194,
264+
.mode_reg = 0x3180,
265+
.status_reg = 0x3198,
266+
.status_bit = 16,
267+
.clkr.hw.init = &(struct clk_init_data){
268+
.name = "pll11",
269+
.parent_data = &(const struct clk_parent_data){
270+
.fw_name = "pxo",
271+
},
272+
.num_parents = 1,
273+
.ops = &clk_pll_ops,
274+
},
275+
};
276+
259277
enum {
260278
P_PXO,
261279
P_PLL8,
@@ -264,6 +282,7 @@ enum {
264282
P_CXO,
265283
P_PLL14,
266284
P_PLL18,
285+
P_PLL11,
267286
};
268287

269288
static const struct parent_map gcc_pxo_pll8_map[] = {
@@ -331,6 +350,44 @@ static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = {
331350
{ .hw = &pll18.clkr.hw },
332351
};
333352

353+
static const struct parent_map gcc_pxo_pll8_pll0_pll14_pll18_pll11_map[] = {
354+
{ P_PXO, 0 },
355+
{ P_PLL8, 4 },
356+
{ P_PLL0, 2 },
357+
{ P_PLL14, 5 },
358+
{ P_PLL18, 1 },
359+
{ P_PLL11, 3 },
360+
};
361+
362+
static const struct clk_parent_data gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = {
363+
{ .fw_name = "pxo" },
364+
{ .hw = &pll8_vote.hw },
365+
{ .hw = &pll0_vote.hw },
366+
{ .hw = &pll14.clkr.hw },
367+
{ .hw = &pll18.clkr.hw },
368+
{ .hw = &pll11.clkr.hw },
369+
370+
};
371+
372+
static const struct parent_map gcc_pxo_pll3_pll0_pll14_pll18_pll11_map[] = {
373+
{ P_PXO, 0 },
374+
{ P_PLL3, 6 },
375+
{ P_PLL0, 2 },
376+
{ P_PLL14, 5 },
377+
{ P_PLL18, 1 },
378+
{ P_PLL11, 3 },
379+
};
380+
381+
static const struct clk_parent_data gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = {
382+
{ .fw_name = "pxo" },
383+
{ .hw = &pll3.clkr.hw },
384+
{ .hw = &pll0_vote.hw },
385+
{ .hw = &pll14.clkr.hw },
386+
{ .hw = &pll18.clkr.hw },
387+
{ .hw = &pll11.clkr.hw },
388+
389+
};
390+
334391
static struct freq_tbl clk_tbl_gsbi_uart[] = {
335392
{ 1843200, P_PLL8, 2, 6, 625 },
336393
{ 3686400, P_PLL8, 2, 12, 625 },
@@ -2824,13 +2881,194 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = {
28242881
},
28252882
};
28262883

2884+
static const struct freq_tbl clk_tbl_ce5_core[] = {
2885+
{ 150000000, P_PLL3, 8, 1, 1 },
2886+
{ 213200000, P_PLL11, 5, 1, 1 },
2887+
{ }
2888+
};
2889+
2890+
static struct clk_dyn_rcg ce5_core_src = {
2891+
.ns_reg[0] = 0x36C4,
2892+
.ns_reg[1] = 0x36C8,
2893+
.bank_reg = 0x36C0,
2894+
.s[0] = {
2895+
.src_sel_shift = 0,
2896+
.parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
2897+
},
2898+
.s[1] = {
2899+
.src_sel_shift = 0,
2900+
.parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
2901+
},
2902+
.p[0] = {
2903+
.pre_div_shift = 3,
2904+
.pre_div_width = 4,
2905+
},
2906+
.p[1] = {
2907+
.pre_div_shift = 3,
2908+
.pre_div_width = 4,
2909+
},
2910+
.mux_sel_bit = 0,
2911+
.freq_tbl = clk_tbl_ce5_core,
2912+
.clkr = {
2913+
.enable_reg = 0x36C0,
2914+
.enable_mask = BIT(1),
2915+
.hw.init = &(struct clk_init_data){
2916+
.name = "ce5_core_src",
2917+
.parent_data = gcc_pxo_pll3_pll0_pll14_pll18_pll11,
2918+
.num_parents = ARRAY_SIZE(gcc_pxo_pll3_pll0_pll14_pll18_pll11),
2919+
.ops = &clk_dyn_rcg_ops,
2920+
},
2921+
},
2922+
};
2923+
2924+
static struct clk_branch ce5_core_clk = {
2925+
.halt_reg = 0x2FDC,
2926+
.halt_bit = 5,
2927+
.hwcg_reg = 0x36CC,
2928+
.hwcg_bit = 6,
2929+
.clkr = {
2930+
.enable_reg = 0x36CC,
2931+
.enable_mask = BIT(4),
2932+
.hw.init = &(struct clk_init_data){
2933+
.name = "ce5_core_clk",
2934+
.parent_hws = (const struct clk_hw*[]){
2935+
&ce5_core_src.clkr.hw,
2936+
},
2937+
.num_parents = 1,
2938+
.ops = &clk_branch_ops,
2939+
.flags = CLK_SET_RATE_PARENT,
2940+
},
2941+
},
2942+
};
2943+
2944+
static const struct freq_tbl clk_tbl_ce5_a_clk[] = {
2945+
{ 160000000, P_PLL0, 5, 1, 1 },
2946+
{ 213200000, P_PLL11, 5, 1, 1 },
2947+
{ }
2948+
};
2949+
2950+
static struct clk_dyn_rcg ce5_a_clk_src = {
2951+
.ns_reg[0] = 0x3d84,
2952+
.ns_reg[1] = 0x3d88,
2953+
.bank_reg = 0x3d80,
2954+
.s[0] = {
2955+
.src_sel_shift = 0,
2956+
.parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
2957+
},
2958+
.s[1] = {
2959+
.src_sel_shift = 0,
2960+
.parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
2961+
},
2962+
.p[0] = {
2963+
.pre_div_shift = 3,
2964+
.pre_div_width = 4,
2965+
},
2966+
.p[1] = {
2967+
.pre_div_shift = 3,
2968+
.pre_div_width = 4,
2969+
},
2970+
.mux_sel_bit = 0,
2971+
.freq_tbl = clk_tbl_ce5_a_clk,
2972+
.clkr = {
2973+
.enable_reg = 0x3d80,
2974+
.enable_mask = BIT(1),
2975+
.hw.init = &(struct clk_init_data){
2976+
.name = "ce5_a_clk_src",
2977+
.parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
2978+
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11),
2979+
.ops = &clk_dyn_rcg_ops,
2980+
},
2981+
},
2982+
};
2983+
2984+
static struct clk_branch ce5_a_clk = {
2985+
.halt_reg = 0x3c20,
2986+
.halt_bit = 12,
2987+
.hwcg_reg = 0x3d8c,
2988+
.hwcg_bit = 6,
2989+
.clkr = {
2990+
.enable_reg = 0x3d8c,
2991+
.enable_mask = BIT(4),
2992+
.hw.init = &(struct clk_init_data){
2993+
.name = "ce5_a_clk",
2994+
.parent_hws = (const struct clk_hw*[]){
2995+
&ce5_a_clk_src.clkr.hw,
2996+
},
2997+
.num_parents = 1,
2998+
.ops = &clk_branch_ops,
2999+
.flags = CLK_SET_RATE_PARENT,
3000+
},
3001+
},
3002+
};
3003+
3004+
static const struct freq_tbl clk_tbl_ce5_h_clk[] = {
3005+
{ 160000000, P_PLL0, 5, 1, 1 },
3006+
{ 213200000, P_PLL11, 5, 1, 1 },
3007+
{ }
3008+
};
3009+
3010+
static struct clk_dyn_rcg ce5_h_clk_src = {
3011+
.ns_reg[0] = 0x3c64,
3012+
.ns_reg[1] = 0x3c68,
3013+
.bank_reg = 0x3c60,
3014+
.s[0] = {
3015+
.src_sel_shift = 0,
3016+
.parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
3017+
},
3018+
.s[1] = {
3019+
.src_sel_shift = 0,
3020+
.parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
3021+
},
3022+
.p[0] = {
3023+
.pre_div_shift = 3,
3024+
.pre_div_width = 4,
3025+
},
3026+
.p[1] = {
3027+
.pre_div_shift = 3,
3028+
.pre_div_width = 4,
3029+
},
3030+
.mux_sel_bit = 0,
3031+
.freq_tbl = clk_tbl_ce5_h_clk,
3032+
.clkr = {
3033+
.enable_reg = 0x3c60,
3034+
.enable_mask = BIT(1),
3035+
.hw.init = &(struct clk_init_data){
3036+
.name = "ce5_h_clk_src",
3037+
.parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
3038+
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11),
3039+
.ops = &clk_dyn_rcg_ops,
3040+
},
3041+
},
3042+
};
3043+
3044+
static struct clk_branch ce5_h_clk = {
3045+
.halt_reg = 0x3c20,
3046+
.halt_bit = 11,
3047+
.hwcg_reg = 0x3c6c,
3048+
.hwcg_bit = 6,
3049+
.clkr = {
3050+
.enable_reg = 0x3c6c,
3051+
.enable_mask = BIT(4),
3052+
.hw.init = &(struct clk_init_data){
3053+
.name = "ce5_h_clk",
3054+
.parent_hws = (const struct clk_hw*[]){
3055+
&ce5_h_clk_src.clkr.hw,
3056+
},
3057+
.num_parents = 1,
3058+
.ops = &clk_branch_ops,
3059+
.flags = CLK_SET_RATE_PARENT,
3060+
},
3061+
},
3062+
};
3063+
28273064
static struct clk_regmap *gcc_ipq806x_clks[] = {
28283065
[PLL0] = &pll0.clkr,
28293066
[PLL0_VOTE] = &pll0_vote,
28303067
[PLL3] = &pll3.clkr,
28313068
[PLL4_VOTE] = &pll4_vote,
28323069
[PLL8] = &pll8.clkr,
28333070
[PLL8_VOTE] = &pll8_vote,
3071+
[PLL11] = &pll11.clkr,
28343072
[PLL14] = &pll14.clkr,
28353073
[PLL14_VOTE] = &pll14_vote,
28363074
[PLL18] = &pll18.clkr,
@@ -2945,6 +3183,12 @@ static struct clk_regmap *gcc_ipq806x_clks[] = {
29453183
[PLL9] = &hfpll0.clkr,
29463184
[PLL10] = &hfpll1.clkr,
29473185
[PLL12] = &hfpll_l2.clkr,
3186+
[CE5_A_CLK_SRC] = &ce5_a_clk_src.clkr,
3187+
[CE5_A_CLK] = &ce5_a_clk.clkr,
3188+
[CE5_H_CLK_SRC] = &ce5_h_clk_src.clkr,
3189+
[CE5_H_CLK] = &ce5_h_clk.clkr,
3190+
[CE5_CORE_CLK_SRC] = &ce5_core_src.clkr,
3191+
[CE5_CORE_CLK] = &ce5_core_clk.clkr,
29483192
};
29493193

29503194
static const struct qcom_reset_map gcc_ipq806x_resets[] = {

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