irqchip/irq-gic-v3-its.c: Force synchronisation when issuing INVALL

Wudi Wang · Marc Zyngier · commit b383a42ca523 · 2021-12-08T11:13:18.000Z
INVALL CMD specifies that the ITS must ensure any caching associated with the interrupt collection defined by ICID is consistent with the LPI configuration tables held in memory for all Redistributors. SYNC is required to ensure that INVALL is executed. Currently, LPI configuration data may be inconsistent with that in the memory within a short period of time after the INVALL command is executed. Signed-off-by: Wudi Wang <wangwudi@hisilicon.com> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Fixes: cc2d321 ("irqchip: GICv3: ITS command queue") Link: https://lore.kernel.org/r/20211208015429.5007-1-zhangshaokun@hisilicon.com
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
@@ -742,7 +742,7 @@ static struct its_collection *its_build_invall_cmd(struct its_node *its,
 
 	its_fixup_cmd(cmd);
 
-	return NULL;
+	return desc->its_invall_cmd.col;
 }
 
 static struct its_vpe *its_build_vinvall_cmd(struct its_node *its,

Original file line number	Diff line number	Diff line change
`@@ -742,7 +742,7 @@ static struct its_collection its_build_invall_cmd(struct its_node its,`
`742`	`742`
`743`	`743`	`its_fixup_cmd(cmd);`
`744`	`744`
`745`		`- return NULL;`
	`745`	`+ return desc->its_invall_cmd.col;`
`746`	`746`	`}`
`747`	`747`
`748`	`748`	`static struct its_vpe its_build_vinvall_cmd(struct its_node its,`