@@ -51,6 +51,19 @@ Optional properties only for parent bus device:
5151- exynos,saturation-ratio: the percentage value which is used to calibrate
5252 the performance count against total cycle count.
5353
54+ Optional properties for the interconnect functionality (QoS frequency
55+ constraints):
56+ - #interconnect-cells: should be 0.
57+ - interconnects: as documented in ../interconnect.txt, describes a path at the
58+ higher level interconnects used by this interconnect provider.
59+ If this interconnect provider is directly linked to a top level interconnect
60+ provider the property contains only one phandle. The provider extends
61+ the interconnect graph by linking its node to a node registered by provider
62+ pointed to by first phandle in the 'interconnects' property.
63+
64+ - samsung,data-clock-ratio: ratio of the data throughput in B/s to minimum data
65+ clock frequency in Hz, default value is 8 when this property is missing.
66+
5467Detailed correlation between sub-blocks and power line according to Exynos SoC:
5568- In case of Exynos3250, there are two power line as following:
5669 VDD_MIF |--- DMC
@@ -135,7 +148,7 @@ Detailed correlation between sub-blocks and power line according to Exynos SoC:
135148 |--- PERIC (Fixed clock rate)
136149 |--- FSYS (Fixed clock rate)
137150
138- Example1 :
151+ Example 1 :
139152 Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
140153 power line (regulator). The MIF (Memory Interface) AXI bus is used to
141154 transfer data between DRAM and CPU and uses the VDD_MIF regulator.
@@ -184,7 +197,7 @@ Example1:
184197 |L5 |200000 |200000 |400000 |300000 | ||1000000 |
185198 ----------------------------------------------------------
186199
187- Example2 :
200+ Example 2 :
188201 The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi
189202 is listed below:
190203
@@ -419,3 +432,57 @@ Example2 :
419432 devfreq = <&bus_leftbus>;
420433 status = "okay";
421434 };
435+
436+ Example 3:
437+ An interconnect path "bus_display -- bus_leftbus -- bus_dmc" on
438+ Exynos4412 SoC with video mixer as an interconnect consumer device.
439+
440+ soc {
441+ bus_dmc: bus_dmc {
442+ compatible = "samsung,exynos-bus";
443+ clocks = <&clock CLK_DIV_DMC>;
444+ clock-names = "bus";
445+ operating-points-v2 = <&bus_dmc_opp_table>;
446+ samsung,data-clock-ratio = <4>;
447+ #interconnect-cells = <0>;
448+ };
449+
450+ bus_leftbus: bus_leftbus {
451+ compatible = "samsung,exynos-bus";
452+ clocks = <&clock CLK_DIV_GDL>;
453+ clock-names = "bus";
454+ operating-points-v2 = <&bus_leftbus_opp_table>;
455+ #interconnect-cells = <0>;
456+ interconnects = <&bus_dmc>;
457+ };
458+
459+ bus_display: bus_display {
460+ compatible = "samsung,exynos-bus";
461+ clocks = <&clock CLK_ACLK160>;
462+ clock-names = "bus";
463+ operating-points-v2 = <&bus_display_opp_table>;
464+ #interconnect-cells = <0>;
465+ interconnects = <&bus_leftbus &bus_dmc>;
466+ };
467+
468+ bus_dmc_opp_table: opp_table1 {
469+ compatible = "operating-points-v2";
470+ /* ... */
471+ }
472+
473+ bus_leftbus_opp_table: opp_table3 {
474+ compatible = "operating-points-v2";
475+ /* ... */
476+ };
477+
478+ bus_display_opp_table: opp_table4 {
479+ compatible = "operating-points-v2";
480+ /* .. */
481+ };
482+
483+ &mixer {
484+ compatible = "samsung,exynos4212-mixer";
485+ interconnects = <&bus_display &bus_dmc>;
486+ /* ... */
487+ };
488+ };
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