Skip to content

Commit b415620

Browse files
Jian Hujbrun3t
Jian Hu
authored and
jbrun3t
committed
dt-bindings: clock: add Amlogic T7 peripherals clock controller
Add DT bindings for the peripheral clock controller of the Amlogic T7 SoC family. Signed-off-by: Jian Hu <jian.hu@amlogic.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20251212022619.3072132-4-jian.hu@amlogic.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
1 parent f5d473e commit b415620

2 files changed

Lines changed: 344 additions & 0 deletions

File tree

‎Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml‎

Lines changed: 116 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,116 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
# Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
3+
%YAML 1.2
4+
---
5+
$id: http://devicetree.org/schemas/clock/amlogic,t7-peripherals-clkc.yaml#
6+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7+
8+
title: Amlogic T7 Peripherals Clock Controller
9+
10+
maintainers:
11+
- Neil Armstrong <neil.armstrong@linaro.org>
12+
- Jerome Brunet <jbrunet@baylibre.com>
13+
- Xianwei Zhao <xianwei.zhao@amlogic.com>
14+
- Jian Hu <jian.hu@amlogic.com>
15+
16+
properties:
17+
compatible:
18+
const: amlogic,t7-peripherals-clkc
19+
20+
reg:
21+
maxItems: 1
22+
23+
'#clock-cells':
24+
const: 1
25+
26+
clocks:
27+
minItems: 14
28+
items:
29+
- description: input oscillator
30+
- description: input sys clk
31+
- description: input fixed pll
32+
- description: input fclk div 2
33+
- description: input fclk div 2p5
34+
- description: input fclk div 3
35+
- description: input fclk div 4
36+
- description: input fclk div 5
37+
- description: input fclk div 7
38+
- description: input hifi pll
39+
- description: input gp0 pll
40+
- description: input gp1 pll
41+
- description: input mpll1
42+
- description: input mpll2
43+
- description: external input rmii oscillator (optional)
44+
- description: input video pll0 (optional)
45+
- description: external pad input for rtc (optional)
46+
47+
clock-names:
48+
minItems: 14
49+
items:
50+
- const: xtal
51+
- const: sys
52+
- const: fix
53+
- const: fdiv2
54+
- const: fdiv2p5
55+
- const: fdiv3
56+
- const: fdiv4
57+
- const: fdiv5
58+
- const: fdiv7
59+
- const: hifi
60+
- const: gp0
61+
- const: gp1
62+
- const: mpll1
63+
- const: mpll2
64+
- const: ext_rmii
65+
- const: vid_pll0
66+
- const: ext_rtc
67+
68+
required:
69+
- compatible
70+
- '#clock-cells'
71+
- reg
72+
- clocks
73+
- clock-names
74+
75+
additionalProperties: false
76+
77+
examples:
78+
- |
79+
apb {
80+
#address-cells = <2>;
81+
#size-cells = <2>;
82+
83+
clkc_periphs:clock-controller@0 {
84+
compatible = "amlogic,t7-peripherals-clkc";
85+
reg = <0 0x0 0 0x1c8>;
86+
#clock-cells = <1>;
87+
clocks = <&xtal>,
88+
<&scmi_clk 13>,
89+
<&scmi_clk 16>,
90+
<&scmi_clk 18>,
91+
<&scmi_clk 20>,
92+
<&scmi_clk 22>,
93+
<&scmi_clk 24>,
94+
<&scmi_clk 26>,
95+
<&scmi_clk 28>,
96+
<&hifi 1>,
97+
<&gp0 1>,
98+
<&gp1 1>,
99+
<&mpll 4>,
100+
<&mpll 6>;
101+
clock-names = "xtal",
102+
"sys",
103+
"fix",
104+
"fdiv2",
105+
"fdiv2p5",
106+
"fdiv3",
107+
"fdiv4",
108+
"fdiv5",
109+
"fdiv7",
110+
"hifi",
111+
"gp0",
112+
"gp1",
113+
"mpll1",
114+
"mpll2";
115+
};
116+
};

‎include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h‎

Lines changed: 228 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,228 @@
1+
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
2+
/*
3+
* Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
4+
*/
5+
6+
#ifndef __T7_PERIPHERALS_CLKC_H
7+
#define __T7_PERIPHERALS_CLKC_H
8+
9+
#define CLKID_RTC_DUALDIV_IN 0
10+
#define CLKID_RTC_DUALDIV_DIV 1
11+
#define CLKID_RTC_DUALDIV_SEL 2
12+
#define CLKID_RTC_DUALDIV 3
13+
#define CLKID_RTC 4
14+
#define CLKID_CECA_DUALDIV_IN 5
15+
#define CLKID_CECA_DUALDIV_DIV 6
16+
#define CLKID_CECA_DUALDIV_SEL 7
17+
#define CLKID_CECA_DUALDIV 8
18+
#define CLKID_CECA 9
19+
#define CLKID_CECB_DUALDIV_IN 10
20+
#define CLKID_CECB_DUALDIV_DIV 11
21+
#define CLKID_CECB_DUALDIV_SEL 12
22+
#define CLKID_CECB_DUALDIV 13
23+
#define CLKID_CECB 14
24+
#define CLKID_SC_SEL 15
25+
#define CLKID_SC_DIV 16
26+
#define CLKID_SC 17
27+
#define CLKID_DSPA_0_SEL 18
28+
#define CLKID_DSPA_0_DIV 19
29+
#define CLKID_DSPA_0 20
30+
#define CLKID_DSPA_1_SEL 21
31+
#define CLKID_DSPA_1_DIV 22
32+
#define CLKID_DSPA_1 23
33+
#define CLKID_DSPA 24
34+
#define CLKID_DSPB_0_SEL 25
35+
#define CLKID_DSPB_0_DIV 26
36+
#define CLKID_DSPB_0 27
37+
#define CLKID_DSPB_1_SEL 28
38+
#define CLKID_DSPB_1_DIV 29
39+
#define CLKID_DSPB_1 30
40+
#define CLKID_DSPB 31
41+
#define CLKID_24M 32
42+
#define CLKID_24M_DIV2 33
43+
#define CLKID_12M 34
44+
#define CLKID_25M_DIV 35
45+
#define CLKID_25M 36
46+
#define CLKID_ANAKIN_0_SEL 37
47+
#define CLKID_ANAKIN_0_DIV 38
48+
#define CLKID_ANAKIN_0 39
49+
#define CLKID_ANAKIN_1_SEL 40
50+
#define CLKID_ANAKIN_1_DIV 41
51+
#define CLKID_ANAKIN_1 42
52+
#define CLKID_ANAKIN_01_SEL 43
53+
#define CLKID_ANAKIN 44
54+
#define CLKID_TS_DIV 45
55+
#define CLKID_TS 46
56+
#define CLKID_MIPI_CSI_PHY_0_SEL 47
57+
#define CLKID_MIPI_CSI_PHY_0_DIV 48
58+
#define CLKID_MIPI_CSI_PHY_0 49
59+
#define CLKID_MIPI_CSI_PHY_1_SEL 50
60+
#define CLKID_MIPI_CSI_PHY_1_DIV 51
61+
#define CLKID_MIPI_CSI_PHY_1 52
62+
#define CLKID_MIPI_CSI_PHY 53
63+
#define CLKID_MIPI_ISP_SEL 54
64+
#define CLKID_MIPI_ISP_DIV 55
65+
#define CLKID_MIPI_ISP 56
66+
#define CLKID_MALI_0_SEL 57
67+
#define CLKID_MALI_0_DIV 58
68+
#define CLKID_MALI_0 59
69+
#define CLKID_MALI_1_SEL 60
70+
#define CLKID_MALI_1_DIV 61
71+
#define CLKID_MALI_1 62
72+
#define CLKID_MALI 63
73+
#define CLKID_ETH_RMII_SEL 64
74+
#define CLKID_ETH_RMII_DIV 65
75+
#define CLKID_ETH_RMII 66
76+
#define CLKID_FCLK_DIV2_DIV8 67
77+
#define CLKID_ETH_125M 68
78+
#define CLKID_SD_EMMC_A_SEL 69
79+
#define CLKID_SD_EMMC_A_DIV 70
80+
#define CLKID_SD_EMMC_A 71
81+
#define CLKID_SD_EMMC_B_SEL 72
82+
#define CLKID_SD_EMMC_B_DIV 73
83+
#define CLKID_SD_EMMC_B 74
84+
#define CLKID_SD_EMMC_C_SEL 75
85+
#define CLKID_SD_EMMC_C_DIV 76
86+
#define CLKID_SD_EMMC_C 77
87+
#define CLKID_SPICC0_SEL 78
88+
#define CLKID_SPICC0_DIV 79
89+
#define CLKID_SPICC0 80
90+
#define CLKID_SPICC1_SEL 81
91+
#define CLKID_SPICC1_DIV 82
92+
#define CLKID_SPICC1 83
93+
#define CLKID_SPICC2_SEL 84
94+
#define CLKID_SPICC2_DIV 85
95+
#define CLKID_SPICC2 86
96+
#define CLKID_SPICC3_SEL 87
97+
#define CLKID_SPICC3_DIV 88
98+
#define CLKID_SPICC3 89
99+
#define CLKID_SPICC4_SEL 90
100+
#define CLKID_SPICC4_DIV 91
101+
#define CLKID_SPICC4 92
102+
#define CLKID_SPICC5_SEL 93
103+
#define CLKID_SPICC5_DIV 94
104+
#define CLKID_SPICC5 95
105+
#define CLKID_SARADC_SEL 96
106+
#define CLKID_SARADC_DIV 97
107+
#define CLKID_SARADC 98
108+
#define CLKID_PWM_A_SEL 99
109+
#define CLKID_PWM_A_DIV 100
110+
#define CLKID_PWM_A 101
111+
#define CLKID_PWM_B_SEL 102
112+
#define CLKID_PWM_B_DIV 103
113+
#define CLKID_PWM_B 104
114+
#define CLKID_PWM_C_SEL 105
115+
#define CLKID_PWM_C_DIV 106
116+
#define CLKID_PWM_C 107
117+
#define CLKID_PWM_D_SEL 108
118+
#define CLKID_PWM_D_DIV 109
119+
#define CLKID_PWM_D 110
120+
#define CLKID_PWM_E_SEL 111
121+
#define CLKID_PWM_E_DIV 112
122+
#define CLKID_PWM_E 113
123+
#define CLKID_PWM_F_SEL 114
124+
#define CLKID_PWM_F_DIV 115
125+
#define CLKID_PWM_F 116
126+
#define CLKID_PWM_AO_A_SEL 117
127+
#define CLKID_PWM_AO_A_DIV 118
128+
#define CLKID_PWM_AO_A 119
129+
#define CLKID_PWM_AO_B_SEL 120
130+
#define CLKID_PWM_AO_B_DIV 121
131+
#define CLKID_PWM_AO_B 122
132+
#define CLKID_PWM_AO_C_SEL 123
133+
#define CLKID_PWM_AO_C_DIV 124
134+
#define CLKID_PWM_AO_C 125
135+
#define CLKID_PWM_AO_D_SEL 126
136+
#define CLKID_PWM_AO_D_DIV 127
137+
#define CLKID_PWM_AO_D 128
138+
#define CLKID_PWM_AO_E_SEL 129
139+
#define CLKID_PWM_AO_E_DIV 130
140+
#define CLKID_PWM_AO_E 131
141+
#define CLKID_PWM_AO_F_SEL 132
142+
#define CLKID_PWM_AO_F_DIV 133
143+
#define CLKID_PWM_AO_F 134
144+
#define CLKID_PWM_AO_G_SEL 135
145+
#define CLKID_PWM_AO_G_DIV 136
146+
#define CLKID_PWM_AO_G 137
147+
#define CLKID_PWM_AO_H_SEL 138
148+
#define CLKID_PWM_AO_H_DIV 139
149+
#define CLKID_PWM_AO_H 140
150+
#define CLKID_SYS_DDR 141
151+
#define CLKID_SYS_DOS 142
152+
#define CLKID_SYS_MIPI_DSI_A 143
153+
#define CLKID_SYS_MIPI_DSI_B 144
154+
#define CLKID_SYS_ETHPHY 145
155+
#define CLKID_SYS_MALI 146
156+
#define CLKID_SYS_AOCPU 147
157+
#define CLKID_SYS_AUCPU 148
158+
#define CLKID_SYS_CEC 149
159+
#define CLKID_SYS_GDC 150
160+
#define CLKID_SYS_DESWARP 151
161+
#define CLKID_SYS_AMPIPE_NAND 152
162+
#define CLKID_SYS_AMPIPE_ETH 153
163+
#define CLKID_SYS_AM2AXI0 154
164+
#define CLKID_SYS_AM2AXI1 155
165+
#define CLKID_SYS_AM2AXI2 156
166+
#define CLKID_SYS_SD_EMMC_A 157
167+
#define CLKID_SYS_SD_EMMC_B 158
168+
#define CLKID_SYS_SD_EMMC_C 159
169+
#define CLKID_SYS_SMARTCARD 160
170+
#define CLKID_SYS_ACODEC 161
171+
#define CLKID_SYS_SPIFC 162
172+
#define CLKID_SYS_MSR_CLK 163
173+
#define CLKID_SYS_IR_CTRL 164
174+
#define CLKID_SYS_AUDIO 165
175+
#define CLKID_SYS_ETH 166
176+
#define CLKID_SYS_UART_A 167
177+
#define CLKID_SYS_UART_B 168
178+
#define CLKID_SYS_UART_C 169
179+
#define CLKID_SYS_UART_D 170
180+
#define CLKID_SYS_UART_E 171
181+
#define CLKID_SYS_UART_F 172
182+
#define CLKID_SYS_AIFIFO 173
183+
#define CLKID_SYS_SPICC2 174
184+
#define CLKID_SYS_SPICC3 175
185+
#define CLKID_SYS_SPICC4 176
186+
#define CLKID_SYS_TS_A73 177
187+
#define CLKID_SYS_TS_A53 178
188+
#define CLKID_SYS_SPICC5 179
189+
#define CLKID_SYS_G2D 180
190+
#define CLKID_SYS_SPICC0 181
191+
#define CLKID_SYS_SPICC1 182
192+
#define CLKID_SYS_PCIE 183
193+
#define CLKID_SYS_USB 184
194+
#define CLKID_SYS_PCIE_PHY 185
195+
#define CLKID_SYS_I2C_AO_A 186
196+
#define CLKID_SYS_I2C_AO_B 187
197+
#define CLKID_SYS_I2C_M_A 188
198+
#define CLKID_SYS_I2C_M_B 189
199+
#define CLKID_SYS_I2C_M_C 190
200+
#define CLKID_SYS_I2C_M_D 191
201+
#define CLKID_SYS_I2C_M_E 192
202+
#define CLKID_SYS_I2C_M_F 193
203+
#define CLKID_SYS_HDMITX_APB 194
204+
#define CLKID_SYS_I2C_S_A 195
205+
#define CLKID_SYS_HDMIRX_PCLK 196
206+
#define CLKID_SYS_MMC_APB 197
207+
#define CLKID_SYS_MIPI_ISP_PCLK 198
208+
#define CLKID_SYS_RSA 199
209+
#define CLKID_SYS_PCLK_SYS_APB 200
210+
#define CLKID_SYS_A73PCLK_APB 201
211+
#define CLKID_SYS_DSPA 202
212+
#define CLKID_SYS_DSPB 203
213+
#define CLKID_SYS_VPU_INTR 204
214+
#define CLKID_SYS_SAR_ADC 205
215+
#define CLKID_SYS_GIC 206
216+
#define CLKID_SYS_TS_GPU 207
217+
#define CLKID_SYS_TS_NNA 208
218+
#define CLKID_SYS_TS_VPU 209
219+
#define CLKID_SYS_TS_HEVC 210
220+
#define CLKID_SYS_PWM_AB 211
221+
#define CLKID_SYS_PWM_CD 212
222+
#define CLKID_SYS_PWM_EF 213
223+
#define CLKID_SYS_PWM_AO_AB 214
224+
#define CLKID_SYS_PWM_AO_CD 215
225+
#define CLKID_SYS_PWM_AO_EF 216
226+
#define CLKID_SYS_PWM_AO_GH 217
227+
228+
#endif /* __T7_PERIPHERALS_CLKC_H */

0 commit comments

Comments
 (0)