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airliedairlied
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Merge tag 'amd-drm-fixes-6.9-2024-04-10' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes
amd-drm-fixes-6.9-2024-04-10: amdgpu: - GPU reset fixes - Fix some confusing logging - UMSCH fix - Aborted suspend fix - DCN 3.5 fixes - S4 fix - MES logging fixes - SMU 14 fixes - SDMA 4.4.2 fix - KASAN fix - SMU 13.0.10 fix - VCN partition fix - GFX11 fixes - DWB fixes - Plane handling fix - FAMS fix - DCN 3.1.6 fix - VSC SDP fixes - OLED panel fix - GFX 11.5 fix amdkfd: - GPU reset fixes Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240411013425.6431-1-alexander.deucher@amd.com
2 parents aaf00e6 + 6dba20d commit b4589db

32 files changed

Lines changed: 652 additions & 127 deletions

‎drivers/gpu/drm/amd/amdgpu/amdgpu.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -210,6 +210,7 @@ extern int amdgpu_async_gfx_ring;
210210
extern int amdgpu_mcbp;
211211
extern int amdgpu_discovery;
212212
extern int amdgpu_mes;
213+
extern int amdgpu_mes_log_enable;
213214
extern int amdgpu_mes_kiq;
214215
extern int amdgpu_noretry;
215216
extern int amdgpu_force_asic_type;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c‎

Lines changed: 15 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -4135,18 +4135,22 @@ int amdgpu_device_init(struct amdgpu_device *adev,
41354135
adev->ip_blocks[i].status.hw = true;
41364136
}
41374137
}
4138+
} else if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10) &&
4139+
!amdgpu_device_has_display_hardware(adev)) {
4140+
r = psp_gpu_reset(adev);
41384141
} else {
4139-
tmp = amdgpu_reset_method;
4140-
/* It should do a default reset when loading or reloading the driver,
4141-
* regardless of the module parameter reset_method.
4142-
*/
4143-
amdgpu_reset_method = AMD_RESET_METHOD_NONE;
4144-
r = amdgpu_asic_reset(adev);
4145-
amdgpu_reset_method = tmp;
4146-
if (r) {
4147-
dev_err(adev->dev, "asic reset on init failed\n");
4148-
goto failed;
4149-
}
4142+
tmp = amdgpu_reset_method;
4143+
/* It should do a default reset when loading or reloading the driver,
4144+
* regardless of the module parameter reset_method.
4145+
*/
4146+
amdgpu_reset_method = AMD_RESET_METHOD_NONE;
4147+
r = amdgpu_asic_reset(adev);
4148+
amdgpu_reset_method = tmp;
4149+
}
4150+
4151+
if (r) {
4152+
dev_err(adev->dev, "asic reset on init failed\n");
4153+
goto failed;
41504154
}
41514155
}
41524156

‎drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1896,6 +1896,7 @@ static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev)
18961896
amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
18971897
break;
18981898
case IP_VERSION(14, 0, 0):
1899+
case IP_VERSION(14, 0, 1):
18991900
amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block);
19001901
break;
19011902
default:

‎drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -195,6 +195,7 @@ int amdgpu_async_gfx_ring = 1;
195195
int amdgpu_mcbp = -1;
196196
int amdgpu_discovery = -1;
197197
int amdgpu_mes;
198+
int amdgpu_mes_log_enable = 0;
198199
int amdgpu_mes_kiq;
199200
int amdgpu_noretry = -1;
200201
int amdgpu_force_asic_type = -1;
@@ -667,6 +668,15 @@ MODULE_PARM_DESC(mes,
667668
"Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
668669
module_param_named(mes, amdgpu_mes, int, 0444);
669670

671+
/**
672+
* DOC: mes_log_enable (int)
673+
* Enable Micro Engine Scheduler log. This is used to enable/disable MES internal log.
674+
* (0 = disabled (default), 1 = enabled)
675+
*/
676+
MODULE_PARM_DESC(mes_log_enable,
677+
"Enable Micro Engine Scheduler log (0 = disabled (default), 1 = enabled)");
678+
module_param_named(mes_log_enable, amdgpu_mes_log_enable, int, 0444);
679+
670680
/**
671681
* DOC: mes_kiq (int)
672682
* Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq.

‎drivers/gpu/drm/amd/amdgpu/amdgpu_job.c‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -304,12 +304,15 @@ static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job)
304304
dma_fence_set_error(finished, -ECANCELED);
305305

306306
if (finished->error < 0) {
307-
DRM_INFO("Skip scheduling IBs!\n");
307+
dev_dbg(adev->dev, "Skip scheduling IBs in ring(%s)",
308+
ring->name);
308309
} else {
309310
r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job,
310311
&fence);
311312
if (r)
312-
DRM_ERROR("Error scheduling IBs (%d)\n", r);
313+
dev_err(adev->dev,
314+
"Error scheduling IBs (%d) in ring(%s)", r,
315+
ring->name);
313316
}
314317

315318
job->job_run_counter++;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -102,7 +102,10 @@ static int amdgpu_mes_event_log_init(struct amdgpu_device *adev)
102102
{
103103
int r;
104104

105-
r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
105+
if (!amdgpu_mes_log_enable)
106+
return 0;
107+
108+
r = amdgpu_bo_create_kernel(adev, AMDGPU_MES_LOG_BUFFER_SIZE, PAGE_SIZE,
106109
AMDGPU_GEM_DOMAIN_GTT,
107110
&adev->mes.event_log_gpu_obj,
108111
&adev->mes.event_log_gpu_addr,
@@ -1549,12 +1552,11 @@ static int amdgpu_debugfs_mes_event_log_show(struct seq_file *m, void *unused)
15491552
uint32_t *mem = (uint32_t *)(adev->mes.event_log_cpu_addr);
15501553

15511554
seq_hex_dump(m, "", DUMP_PREFIX_OFFSET, 32, 4,
1552-
mem, PAGE_SIZE, false);
1555+
mem, AMDGPU_MES_LOG_BUFFER_SIZE, false);
15531556

15541557
return 0;
15551558
}
15561559

1557-
15581560
DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_mes_event_log);
15591561

15601562
#endif
@@ -1565,7 +1567,7 @@ void amdgpu_debugfs_mes_event_log_init(struct amdgpu_device *adev)
15651567
#if defined(CONFIG_DEBUG_FS)
15661568
struct drm_minor *minor = adev_to_drm(adev)->primary;
15671569
struct dentry *root = minor->debugfs_root;
1568-
if (adev->enable_mes)
1570+
if (adev->enable_mes && amdgpu_mes_log_enable)
15691571
debugfs_create_file("amdgpu_mes_event_log", 0444, root,
15701572
adev, &amdgpu_debugfs_mes_event_log_fops);
15711573

‎drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,7 @@ enum amdgpu_mes_priority_level {
5252

5353
#define AMDGPU_MES_PROC_CTX_SIZE 0x1000 /* one page area */
5454
#define AMDGPU_MES_GANG_CTX_SIZE 0x1000 /* one page area */
55+
#define AMDGPU_MES_LOG_BUFFER_SIZE 0x4000 /* Maximu log buffer size for MES */
5556

5657
struct amdgpu_mes_funcs;
5758

‎drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c‎

Lines changed: 11 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -62,6 +62,11 @@ void aqua_vanjaram_doorbell_index_init(struct amdgpu_device *adev)
6262
adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT << 1;
6363
}
6464

65+
static bool aqua_vanjaram_xcp_vcn_shared(struct amdgpu_device *adev)
66+
{
67+
return (adev->xcp_mgr->num_xcps > adev->vcn.num_vcn_inst);
68+
}
69+
6570
static void aqua_vanjaram_set_xcp_id(struct amdgpu_device *adev,
6671
uint32_t inst_idx, struct amdgpu_ring *ring)
6772
{
@@ -87,7 +92,7 @@ static void aqua_vanjaram_set_xcp_id(struct amdgpu_device *adev,
8792
case AMDGPU_RING_TYPE_VCN_ENC:
8893
case AMDGPU_RING_TYPE_VCN_JPEG:
8994
ip_blk = AMDGPU_XCP_VCN;
90-
if (adev->xcp_mgr->mode == AMDGPU_CPX_PARTITION_MODE)
95+
if (aqua_vanjaram_xcp_vcn_shared(adev))
9196
inst_mask = 1 << (inst_idx * 2);
9297
break;
9398
default:
@@ -140,10 +145,12 @@ static int aqua_vanjaram_xcp_sched_list_update(
140145

141146
aqua_vanjaram_xcp_gpu_sched_update(adev, ring, ring->xcp_id);
142147

143-
/* VCN is shared by two partitions under CPX MODE */
148+
/* VCN may be shared by two partitions under CPX MODE in certain
149+
* configs.
150+
*/
144151
if ((ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC ||
145-
ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) &&
146-
adev->xcp_mgr->mode == AMDGPU_CPX_PARTITION_MODE)
152+
ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) &&
153+
aqua_vanjaram_xcp_vcn_shared(adev))
147154
aqua_vanjaram_xcp_gpu_sched_update(adev, ring, ring->xcp_id + 1);
148155
}
149156

‎drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1635,7 +1635,7 @@ static void gfx_v11_0_setup_rb(struct amdgpu_device *adev)
16351635
active_rb_bitmap |= (0x3 << (i * rb_bitmap_width_per_sa));
16361636
}
16371637

1638-
active_rb_bitmap |= global_active_rb_bitmap;
1638+
active_rb_bitmap &= global_active_rb_bitmap;
16391639
adev->gfx.config.backend_enable_mask = active_rb_bitmap;
16401640
adev->gfx.config.num_rbs = hweight32(active_rb_bitmap);
16411641
}
@@ -5465,6 +5465,7 @@ static void gfx_v11_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
54655465
/* Make sure that we can't skip the SET_Q_MODE packets when the VM
54665466
* changed in any way.
54675467
*/
5468+
ring->set_q_mode_offs = 0;
54685469
ring->set_q_mode_ptr = NULL;
54695470
}
54705471

‎drivers/gpu/drm/amd/amdgpu/mes_v11_0.c‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -411,8 +411,11 @@ static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
411411
mes_set_hw_res_pkt.enable_reg_active_poll = 1;
412412
mes_set_hw_res_pkt.enable_level_process_quantum_check = 1;
413413
mes_set_hw_res_pkt.oversubscription_timer = 50;
414-
mes_set_hw_res_pkt.enable_mes_event_int_logging = 1;
415-
mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes->event_log_gpu_addr;
414+
if (amdgpu_mes_log_enable) {
415+
mes_set_hw_res_pkt.enable_mes_event_int_logging = 1;
416+
mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr =
417+
mes->event_log_gpu_addr;
418+
}
416419

417420
return mes_v11_0_submit_pkt_and_poll_completion(mes,
418421
&mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),

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