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author
Paolo Abeni
committed
Merge branch 'net-mvpp2-rss-fixes'
Sven Auhagen says: ==================== net: mvpp2: rss fixes This patch series fixes up some rss problems in the mvpp2 driver. The classifier is missing some fragmentation flags, the parser has the QinQ headers switched and the PPPoE Layer 4 detecion is not working correctly. This is leading to no or bad rss for the default settings. ==================== Link: https://lore.kernel.org/r/20230325163903.ofefgus43x66as7i@Svens-MacBookPro.local Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2 parents ebd3b82 + 031a416 commit b4c66d7

2 files changed

Lines changed: 54 additions & 62 deletions

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‎drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c‎

Lines changed: 18 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -62,35 +62,38 @@ static const struct mvpp2_cls_flow cls_flows[MVPP2_N_PRS_FLOWS] = {
6262
MVPP2_DEF_FLOW(MVPP22_FLOW_TCP4, MVPP2_FL_IP4_TCP_FRAG_UNTAG,
6363
MVPP22_CLS_HEK_IP4_2T,
6464
MVPP2_PRS_RI_VLAN_NONE | MVPP2_PRS_RI_L3_IP4 |
65-
MVPP2_PRS_RI_L4_TCP,
65+
MVPP2_PRS_RI_IP_FRAG_TRUE | MVPP2_PRS_RI_L4_TCP,
6666
MVPP2_PRS_IP_MASK | MVPP2_PRS_RI_VLAN_MASK),
6767

6868
MVPP2_DEF_FLOW(MVPP22_FLOW_TCP4, MVPP2_FL_IP4_TCP_FRAG_UNTAG,
6969
MVPP22_CLS_HEK_IP4_2T,
7070
MVPP2_PRS_RI_VLAN_NONE | MVPP2_PRS_RI_L3_IP4_OPT |
71-
MVPP2_PRS_RI_L4_TCP,
71+
MVPP2_PRS_RI_IP_FRAG_TRUE | MVPP2_PRS_RI_L4_TCP,
7272
MVPP2_PRS_IP_MASK | MVPP2_PRS_RI_VLAN_MASK),
7373

7474
MVPP2_DEF_FLOW(MVPP22_FLOW_TCP4, MVPP2_FL_IP4_TCP_FRAG_UNTAG,
7575
MVPP22_CLS_HEK_IP4_2T,
7676
MVPP2_PRS_RI_VLAN_NONE | MVPP2_PRS_RI_L3_IP4_OTHER |
77-
MVPP2_PRS_RI_L4_TCP,
77+
MVPP2_PRS_RI_IP_FRAG_TRUE | MVPP2_PRS_RI_L4_TCP,
7878
MVPP2_PRS_IP_MASK | MVPP2_PRS_RI_VLAN_MASK),
7979

8080
/* TCP over IPv4 flows, fragmented, with vlan tag */
8181
MVPP2_DEF_FLOW(MVPP22_FLOW_TCP4, MVPP2_FL_IP4_TCP_FRAG_TAG,
8282
MVPP22_CLS_HEK_IP4_2T | MVPP22_CLS_HEK_TAGGED,
83-
MVPP2_PRS_RI_L3_IP4 | MVPP2_PRS_RI_L4_TCP,
83+
MVPP2_PRS_RI_L3_IP4 | MVPP2_PRS_RI_IP_FRAG_TRUE |
84+
MVPP2_PRS_RI_L4_TCP,
8485
MVPP2_PRS_IP_MASK),
8586

8687
MVPP2_DEF_FLOW(MVPP22_FLOW_TCP4, MVPP2_FL_IP4_TCP_FRAG_TAG,
8788
MVPP22_CLS_HEK_IP4_2T | MVPP22_CLS_HEK_TAGGED,
88-
MVPP2_PRS_RI_L3_IP4_OPT | MVPP2_PRS_RI_L4_TCP,
89+
MVPP2_PRS_RI_L3_IP4_OPT | MVPP2_PRS_RI_IP_FRAG_TRUE |
90+
MVPP2_PRS_RI_L4_TCP,
8991
MVPP2_PRS_IP_MASK),
9092

9193
MVPP2_DEF_FLOW(MVPP22_FLOW_TCP4, MVPP2_FL_IP4_TCP_FRAG_TAG,
9294
MVPP22_CLS_HEK_IP4_2T | MVPP22_CLS_HEK_TAGGED,
93-
MVPP2_PRS_RI_L3_IP4_OTHER | MVPP2_PRS_RI_L4_TCP,
95+
MVPP2_PRS_RI_L3_IP4_OTHER | MVPP2_PRS_RI_IP_FRAG_TRUE |
96+
MVPP2_PRS_RI_L4_TCP,
9497
MVPP2_PRS_IP_MASK),
9598

9699
/* UDP over IPv4 flows, Not fragmented, no vlan tag */
@@ -132,35 +135,38 @@ static const struct mvpp2_cls_flow cls_flows[MVPP2_N_PRS_FLOWS] = {
132135
MVPP2_DEF_FLOW(MVPP22_FLOW_UDP4, MVPP2_FL_IP4_UDP_FRAG_UNTAG,
133136
MVPP22_CLS_HEK_IP4_2T,
134137
MVPP2_PRS_RI_VLAN_NONE | MVPP2_PRS_RI_L3_IP4 |
135-
MVPP2_PRS_RI_L4_UDP,
138+
MVPP2_PRS_RI_IP_FRAG_TRUE | MVPP2_PRS_RI_L4_UDP,
136139
MVPP2_PRS_IP_MASK | MVPP2_PRS_RI_VLAN_MASK),
137140

138141
MVPP2_DEF_FLOW(MVPP22_FLOW_UDP4, MVPP2_FL_IP4_UDP_FRAG_UNTAG,
139142
MVPP22_CLS_HEK_IP4_2T,
140143
MVPP2_PRS_RI_VLAN_NONE | MVPP2_PRS_RI_L3_IP4_OPT |
141-
MVPP2_PRS_RI_L4_UDP,
144+
MVPP2_PRS_RI_IP_FRAG_TRUE | MVPP2_PRS_RI_L4_UDP,
142145
MVPP2_PRS_IP_MASK | MVPP2_PRS_RI_VLAN_MASK),
143146

144147
MVPP2_DEF_FLOW(MVPP22_FLOW_UDP4, MVPP2_FL_IP4_UDP_FRAG_UNTAG,
145148
MVPP22_CLS_HEK_IP4_2T,
146149
MVPP2_PRS_RI_VLAN_NONE | MVPP2_PRS_RI_L3_IP4_OTHER |
147-
MVPP2_PRS_RI_L4_UDP,
150+
MVPP2_PRS_RI_IP_FRAG_TRUE | MVPP2_PRS_RI_L4_UDP,
148151
MVPP2_PRS_IP_MASK | MVPP2_PRS_RI_VLAN_MASK),
149152

150153
/* UDP over IPv4 flows, fragmented, with vlan tag */
151154
MVPP2_DEF_FLOW(MVPP22_FLOW_UDP4, MVPP2_FL_IP4_UDP_FRAG_TAG,
152155
MVPP22_CLS_HEK_IP4_2T | MVPP22_CLS_HEK_TAGGED,
153-
MVPP2_PRS_RI_L3_IP4 | MVPP2_PRS_RI_L4_UDP,
156+
MVPP2_PRS_RI_L3_IP4 | MVPP2_PRS_RI_IP_FRAG_TRUE |
157+
MVPP2_PRS_RI_L4_UDP,
154158
MVPP2_PRS_IP_MASK),
155159

156160
MVPP2_DEF_FLOW(MVPP22_FLOW_UDP4, MVPP2_FL_IP4_UDP_FRAG_TAG,
157161
MVPP22_CLS_HEK_IP4_2T | MVPP22_CLS_HEK_TAGGED,
158-
MVPP2_PRS_RI_L3_IP4_OPT | MVPP2_PRS_RI_L4_UDP,
162+
MVPP2_PRS_RI_L3_IP4_OPT | MVPP2_PRS_RI_IP_FRAG_TRUE |
163+
MVPP2_PRS_RI_L4_UDP,
159164
MVPP2_PRS_IP_MASK),
160165

161166
MVPP2_DEF_FLOW(MVPP22_FLOW_UDP4, MVPP2_FL_IP4_UDP_FRAG_TAG,
162167
MVPP22_CLS_HEK_IP4_2T | MVPP22_CLS_HEK_TAGGED,
163-
MVPP2_PRS_RI_L3_IP4_OTHER | MVPP2_PRS_RI_L4_UDP,
168+
MVPP2_PRS_RI_L3_IP4_OTHER | MVPP2_PRS_RI_IP_FRAG_TRUE |
169+
MVPP2_PRS_RI_L4_UDP,
164170
MVPP2_PRS_IP_MASK),
165171

166172
/* TCP over IPv6 flows, not fragmented, no vlan tag */

‎drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c‎

Lines changed: 36 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -1539,8 +1539,8 @@ static int mvpp2_prs_vlan_init(struct platform_device *pdev, struct mvpp2 *priv)
15391539
if (!priv->prs_double_vlans)
15401540
return -ENOMEM;
15411541

1542-
/* Double VLAN: 0x8100, 0x88A8 */
1543-
err = mvpp2_prs_double_vlan_add(priv, ETH_P_8021Q, ETH_P_8021AD,
1542+
/* Double VLAN: 0x88A8, 0x8100 */
1543+
err = mvpp2_prs_double_vlan_add(priv, ETH_P_8021AD, ETH_P_8021Q,
15441544
MVPP2_PRS_PORT_MASK);
15451545
if (err)
15461546
return err;
@@ -1607,59 +1607,45 @@ static int mvpp2_prs_vlan_init(struct platform_device *pdev, struct mvpp2 *priv)
16071607
static int mvpp2_prs_pppoe_init(struct mvpp2 *priv)
16081608
{
16091609
struct mvpp2_prs_entry pe;
1610-
int tid;
1611-
1612-
/* IPv4 over PPPoE with options */
1613-
tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1614-
MVPP2_PE_LAST_FREE_TID);
1615-
if (tid < 0)
1616-
return tid;
1617-
1618-
memset(&pe, 0, sizeof(pe));
1619-
mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
1620-
pe.index = tid;
1621-
1622-
mvpp2_prs_match_etype(&pe, 0, PPP_IP);
1623-
1624-
mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
1625-
mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT,
1626-
MVPP2_PRS_RI_L3_PROTO_MASK);
1627-
/* goto ipv4 dest-address (skip eth_type + IP-header-size - 4) */
1628-
mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN +
1629-
sizeof(struct iphdr) - 4,
1630-
MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1631-
/* Set L3 offset */
1632-
mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1633-
MVPP2_ETH_TYPE_LEN,
1634-
MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
1635-
1636-
/* Update shadow table and hw entry */
1637-
mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE);
1638-
mvpp2_prs_hw_write(priv, &pe);
1610+
int tid, ihl;
16391611

1640-
/* IPv4 over PPPoE without options */
1641-
tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1642-
MVPP2_PE_LAST_FREE_TID);
1643-
if (tid < 0)
1644-
return tid;
1612+
/* IPv4 over PPPoE with header length >= 5 */
1613+
for (ihl = MVPP2_PRS_IPV4_IHL_MIN; ihl <= MVPP2_PRS_IPV4_IHL_MAX; ihl++) {
1614+
tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1615+
MVPP2_PE_LAST_FREE_TID);
1616+
if (tid < 0)
1617+
return tid;
16451618

1646-
pe.index = tid;
1619+
memset(&pe, 0, sizeof(pe));
1620+
mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
1621+
pe.index = tid;
16471622

1648-
mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
1649-
MVPP2_PRS_IPV4_HEAD |
1650-
MVPP2_PRS_IPV4_IHL_MIN,
1651-
MVPP2_PRS_IPV4_HEAD_MASK |
1652-
MVPP2_PRS_IPV4_IHL_MASK);
1623+
mvpp2_prs_match_etype(&pe, 0, PPP_IP);
1624+
mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
1625+
MVPP2_PRS_IPV4_HEAD | ihl,
1626+
MVPP2_PRS_IPV4_HEAD_MASK |
1627+
MVPP2_PRS_IPV4_IHL_MASK);
16531628

1654-
/* Clear ri before updating */
1655-
pe.sram[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
1656-
pe.sram[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
1657-
mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
1658-
MVPP2_PRS_RI_L3_PROTO_MASK);
1629+
mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
1630+
mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
1631+
MVPP2_PRS_RI_L3_PROTO_MASK);
1632+
/* goto ipv4 dst-address (skip eth_type + IP-header-size - 4) */
1633+
mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN +
1634+
sizeof(struct iphdr) - 4,
1635+
MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1636+
/* Set L3 offset */
1637+
mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1638+
MVPP2_ETH_TYPE_LEN,
1639+
MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
1640+
/* Set L4 offset */
1641+
mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4,
1642+
MVPP2_ETH_TYPE_LEN + (ihl * 4),
1643+
MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
16591644

1660-
/* Update shadow table and hw entry */
1661-
mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE);
1662-
mvpp2_prs_hw_write(priv, &pe);
1645+
/* Update shadow table and hw entry */
1646+
mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE);
1647+
mvpp2_prs_hw_write(priv, &pe);
1648+
}
16631649

16641650
/* IPv6 over PPPoE */
16651651
tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,

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