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Merge branch 'for-next/perf' into for-next/core
* for-next/perf: (25 commits) perf/marvell: Fix !CONFIG_OF build for CN10K DDR PMU driver drivers/perf: Add Apple icestorm/firestorm CPU PMU driver drivers/perf: arm_pmu: Handle 47 bit counters arm64: perf: Consistently make all event numbers as 16-bits arm64: perf: Expose some Armv9 common events under sysfs perf/marvell: cn10k DDR perf event core ownership perf/marvell: cn10k DDR perfmon event overflow handling perf/marvell: CN10k DDR performance monitor support dt-bindings: perf: marvell: cn10k ddr performance monitor perf/arm-cmn: Update watchpoint format perf/arm-cmn: Hide XP PUB events for CMN-600 perf: replace bitmap_weight with bitmap_empty where appropriate perf: Replace acpi_bus_get_device() perf/marvell_cn10k: Fix unused variable warning when W=1 and CONFIG_OF=n perf/arm-cmn: Make arm_cmn_debugfs static perf: MARVELL_CN10K_TAD_PMU should depend on ARCH_THUNDER perf/arm-ccn: Use platform_get_irq() to get the interrupt irqchip/apple-aic: Move PMU-specific registers to their own include file arm64: dts: apple: Add t8303 PMU nodes arm64: dts: apple: Add t8103 PMU interrupt affinities ...
2 parents 292ca2d + 6676a42 commit b5ef94f

23 files changed

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‎Documentation/devicetree/bindings/arm/pmu.yaml‎

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items:
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- enum:
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- apm,potenza-pmu
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- apple,firestorm-pmu
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- apple,icestorm-pmu
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- arm,armv8-pmuv3 # Only for s/w models
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- arm,arm1136-pmu
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- arm,arm1176-pmu

‎Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml‎

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- 1: virtual HV timer
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- 2: physical guest timer
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- 3: virtual guest timer
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- 4: 'efficient' CPU PMU
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- 5: 'performance' CPU PMU
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The 3rd cell contains the interrupt flags. This is normally
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IRQ_TYPE_LEVEL_HIGH (4).
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power-domains:
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maxItems: 1
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affinities:
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type: object
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additionalProperties: false
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description:
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FIQ affinity can be expressed as a single "affinities" node,
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containing a set of sub-nodes, one per FIQ with a non-default
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affinity.
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patternProperties:
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"^.+-affinity$":
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type: object
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additionalProperties: false
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properties:
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apple,fiq-index:
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description:
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The interrupt number specified as a FIQ, and for which
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the affinity is not the default.
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 5
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cpus:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description:
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Should be a list of phandles to CPU nodes (as described in
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Documentation/devicetree/bindings/arm/cpus.yaml).
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required:
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- fiq-index
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- cpus
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required:
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- compatible
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- '#interrupt-cells'

‎Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/perf/marvell-cn10k-ddr.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Marvell CN10K DDR performance monitor
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maintainers:
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- Bharat Bhushan <bbhushan2@marvell.com>
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properties:
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compatible:
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items:
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- enum:
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- marvell,cn10k-ddr-pmu
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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pmu@87e1c0000000 {
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compatible = "marvell,cn10k-ddr-pmu";
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reg = <0x87e1 0xc0000000 0x0 0x10000>;
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};
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};

‎arch/arm64/boot/dts/apple/t8103.dtsi‎

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<AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>;
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};
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pmu-e {
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compatible = "apple,icestorm-pmu";
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interrupt-parent = <&aic>;
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interrupts = <AIC_FIQ AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>;
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};
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pmu-p {
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compatible = "apple,firestorm-pmu";
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interrupt-parent = <&aic>;
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interrupts = <AIC_FIQ AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>;
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};
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clkref: clock-ref {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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interrupt-controller;
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reg = <0x2 0x3b100000 0x0 0x8000>;
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power-domains = <&ps_aic>;
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affinities {
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e-core-pmu-affinity {
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apple,fiq-index = <AIC_CPU_PMU_E>;
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cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
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};
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p-core-pmu-affinity {
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apple,fiq-index = <AIC_CPU_PMU_P>;
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cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
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};
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};
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};
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pmgr: power-management@23b700000 {

‎arch/arm64/include/asm/apple_m1_pmu.h‎

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// SPDX-License-Identifier: GPL-2.0
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#ifndef __ASM_APPLE_M1_PMU_h
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#define __ASM_APPLE_M1_PMU_h
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#include <linux/bits.h>
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#include <asm/sysreg.h>
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/* Counters */
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#define SYS_IMP_APL_PMC0_EL1 sys_reg(3, 2, 15, 0, 0)
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#define SYS_IMP_APL_PMC1_EL1 sys_reg(3, 2, 15, 1, 0)
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#define SYS_IMP_APL_PMC2_EL1 sys_reg(3, 2, 15, 2, 0)
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#define SYS_IMP_APL_PMC3_EL1 sys_reg(3, 2, 15, 3, 0)
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#define SYS_IMP_APL_PMC4_EL1 sys_reg(3, 2, 15, 4, 0)
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#define SYS_IMP_APL_PMC5_EL1 sys_reg(3, 2, 15, 5, 0)
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#define SYS_IMP_APL_PMC6_EL1 sys_reg(3, 2, 15, 6, 0)
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#define SYS_IMP_APL_PMC7_EL1 sys_reg(3, 2, 15, 7, 0)
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#define SYS_IMP_APL_PMC8_EL1 sys_reg(3, 2, 15, 9, 0)
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#define SYS_IMP_APL_PMC9_EL1 sys_reg(3, 2, 15, 10, 0)
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/* Core PMC control register */
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#define SYS_IMP_APL_PMCR0_EL1 sys_reg(3, 1, 15, 0, 0)
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#define PMCR0_CNT_ENABLE_0_7 GENMASK(7, 0)
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#define PMCR0_IMODE GENMASK(10, 8)
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#define PMCR0_IMODE_OFF 0
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#define PMCR0_IMODE_PMI 1
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#define PMCR0_IMODE_AIC 2
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#define PMCR0_IMODE_HALT 3
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#define PMCR0_IMODE_FIQ 4
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#define PMCR0_IACT BIT(11)
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#define PMCR0_PMI_ENABLE_0_7 GENMASK(19, 12)
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#define PMCR0_STOP_CNT_ON_PMI BIT(20)
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#define PMCR0_CNT_GLOB_L2C_EVT BIT(21)
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#define PMCR0_DEFER_PMI_TO_ERET BIT(22)
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#define PMCR0_ALLOW_CNT_EN_EL0 BIT(30)
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#define PMCR0_CNT_ENABLE_8_9 GENMASK(33, 32)
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#define PMCR0_PMI_ENABLE_8_9 GENMASK(45, 44)
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#define SYS_IMP_APL_PMCR1_EL1 sys_reg(3, 1, 15, 1, 0)
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#define PMCR1_COUNT_A64_EL0_0_7 GENMASK(15, 8)
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#define PMCR1_COUNT_A64_EL1_0_7 GENMASK(23, 16)
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#define PMCR1_COUNT_A64_EL0_8_9 GENMASK(41, 40)
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#define PMCR1_COUNT_A64_EL1_8_9 GENMASK(49, 48)
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#define SYS_IMP_APL_PMCR2_EL1 sys_reg(3, 1, 15, 2, 0)
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#define SYS_IMP_APL_PMCR3_EL1 sys_reg(3, 1, 15, 3, 0)
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#define SYS_IMP_APL_PMCR4_EL1 sys_reg(3, 1, 15, 4, 0)
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#define SYS_IMP_APL_PMESR0_EL1 sys_reg(3, 1, 15, 5, 0)
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#define PMESR0_EVT_CNT_2 GENMASK(7, 0)
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#define PMESR0_EVT_CNT_3 GENMASK(15, 8)
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#define PMESR0_EVT_CNT_4 GENMASK(23, 16)
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#define PMESR0_EVT_CNT_5 GENMASK(31, 24)
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#define SYS_IMP_APL_PMESR1_EL1 sys_reg(3, 1, 15, 6, 0)
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#define PMESR1_EVT_CNT_6 GENMASK(7, 0)
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#define PMESR1_EVT_CNT_7 GENMASK(15, 8)
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#define PMESR1_EVT_CNT_8 GENMASK(23, 16)
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#define PMESR1_EVT_CNT_9 GENMASK(31, 24)
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#define SYS_IMP_APL_PMSR_EL1 sys_reg(3, 1, 15, 13, 0)
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#define PMSR_OVERFLOW GENMASK(9, 0)
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#endif /* __ASM_APPLE_M1_PMU_h */

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