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Merge tag 'mips_5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS upates from Thomas Bogendoerfer: - improvements for Loongson64 - extended ingenic support - removal of not maintained paravirt system type - cleanups and fixes * tag 'mips_5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (81 commits) MIPS: SGI-IP27: always enable NUMA in Kconfig MAINTAINERS: Update KVM/MIPS maintainers MIPS: Update default config file for Loongson-3 MIPS: KVM: Add kvm guest support for Loongson-3 dt-bindings: mips: Document Loongson kvm guest board MIPS: handle Loongson-specific GSExc exception MIPS: add definitions for Loongson-specific CP0.Diag1 register MIPS: only register FTLBPar exception handler for supported models MIPS: ingenic: Hardcode mem size for qi,lb60 board MIPS: DTS: ingenic/qi,lb60: Add model and memory node MIPS: ingenic: Use fw_passed_dtb even if CONFIG_BUILTIN_DTB MIPS: head.S: Init fw_passed_dtb to builtin DTB of: address: Fix parser address/size cells initialization of_address: Guard of_bus_pci_get_flags with CONFIG_PCI MIPS: DTS: Fix number of msi vectors for Loongson64G MIPS: Loongson64: Add ISA node for LS7A PCH MIPS: Loongson64: DTS: Fix ISA and PCI I/O ranges for RS780E PCH MIPS: Loongson64: Enlarge IO_SPACE_LIMIT MIPS: Loongson64: Process ISA Node in DeviceTree of_address: Add bus type match for pci ranges parser ...
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Lines changed: 3139 additions & 1608 deletions

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‎Documentation/devicetree/bindings/bus/mti,mips-cdmm.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bus/mti,mips-cdmm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MIPS Common Device Memory Map
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description: |
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Defines a location of the MIPS Common Device Memory Map registers.
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maintainers:
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- James Hogan <jhogan@kernel.org>
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properties:
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compatible:
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const: mti,mips-cdmm
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reg:
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description: |
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Base address and size of an unoccupied memory region, which will be
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used to map the MIPS CDMM registers block.
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maxItems: 1
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required:
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- compatible
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- reg
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examples:
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- |
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cdmm@1bde8000 {
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compatible = "mti,mips-cdmm";
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reg = <0x1bde8000 0x8000>;
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};
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...

‎Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt‎

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‎Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml‎

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# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MIPS Global Interrupt Controller
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maintainers:
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- Paul Burton <paulburton@kernel.org>
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- Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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description: |
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The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
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It also supports local (per-processor) interrupts and software-generated
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interrupts which can be used as IPIs. The GIC also includes a free-running
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global timer, per-CPU count/compare timers, and a watchdog.
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properties:
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compatible:
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const: mti,gic
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"#interrupt-cells":
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const: 3
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description: |
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The 1st cell is the type of interrupt: local or shared defined in the
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file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the
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GIC interrupt number. The 3d cell encodes the interrupt flags setting up
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the IRQ trigger modes, which are defined in the file
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'dt-bindings/interrupt-controller/irq.h'.
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reg:
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description: |
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Base address and length of the GIC registers space. If not present,
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the base address reported by the hardware GCR_GIC_BASE will be used.
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maxItems: 1
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interrupt-controller: true
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mti,reserved-cpu-vectors:
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description: |
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Specifies the list of CPU interrupt vectors to which the GIC may not
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route interrupts. This property is ignored if the CPU is started in EIC
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mode.
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allOf:
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- $ref: /schemas/types.yaml#definitions/uint32-array
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- minItems: 1
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maxItems: 6
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uniqueItems: true
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items:
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minimum: 2
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maximum: 7
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mti,reserved-ipi-vectors:
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description: |
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Specifies the range of GIC interrupts that are reserved for IPIs.
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It accepts two values: the 1st is the starting interrupt and the 2nd is
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the size of the reserved range. If not specified, the driver will
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allocate the last (2 * number of VPEs in the system).
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allOf:
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- $ref: /schemas/types.yaml#definitions/uint32-array
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- items:
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- minimum: 0
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maximum: 254
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- minimum: 2
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maximum: 254
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timer:
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type: object
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description: |
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MIPS GIC includes a free-running global timer, per-CPU count/compare
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timers, and a watchdog. Currently only the GIC Timer is supported.
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properties:
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compatible:
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const: mti,gic-timer
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interrupts:
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description: |
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Interrupt for the GIC local timer, so normally it's suppose to be of
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<GIC_LOCAL X IRQ_TYPE_NONE> format.
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maxItems: 1
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clocks:
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maxItems: 1
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clock-frequency: true
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required:
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- compatible
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- interrupts
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oneOf:
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- required:
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- clocks
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- required:
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- clock-frequency
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additionalProperties: false
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unevaluatedProperties: false
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required:
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- compatible
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- "#interrupt-cells"
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- interrupt-controller
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examples:
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- |
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#include <dt-bindings/interrupt-controller/mips-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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interrupt-controller@1bdc0000 {
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compatible = "mti,gic";
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reg = <0x1bdc0000 0x20000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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mti,reserved-cpu-vectors = <7>;
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mti,reserved-ipi-vectors = <40 8>;
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timer {
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compatible = "mti,gic-timer";
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interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
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clock-frequency = <50000000>;
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};
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};
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- |
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#include <dt-bindings/interrupt-controller/mips-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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interrupt-controller@1bdc0000 {
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compatible = "mti,gic";
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reg = <0x1bdc0000 0x20000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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timer {
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compatible = "mti,gic-timer";
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interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
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clocks = <&cpu_pll>;
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};
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};
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- |
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interrupt-controller {
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compatible = "mti,gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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...

‎Documentation/devicetree/bindings/mips/ingenic/devices.yaml‎

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maintainers:
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- 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
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description: |
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description:
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Devices with a Ingenic XBurst CPU shall have the following properties.
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properties:
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- const: qi,lb60
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- const: ingenic,jz4740
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- description: YLM RetroMini RS-90
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items:
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- const: ylm,rs90
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- const: ingenic,jz4725b
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- description: Game Consoles Worldwide GCW Zero
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items:
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- const: gcw,zero
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- const: img,ci20
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- const: ingenic,jz4780
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- description: YSH & ATIL General Board CU Neo
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- description: YSH & ATIL General Board, CU1000 Module with Neo Backplane
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items:
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- const: yna,cu1000-neo
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- const: ingenic,x1000
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- const: ingenic,x1000e
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- description: YSH & ATIL General Board, CU1830 Module with Neo Backplane
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items:
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- const: yna,cu1830-neo
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- const: ingenic,x1830
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...

‎Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mips/ingenic/ingenic,cpu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Bindings for Ingenic XBurst family CPUs
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maintainers:
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- 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
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description:
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Ingenic XBurst family CPUs shall have the following properties.
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properties:
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compatible:
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oneOf:
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- description: Ingenic XBurst®1 CPU Cores
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enum:
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- ingenic,xburst-mxu1.0
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- ingenic,xburst-fpu1.0-mxu1.1
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- ingenic,xburst-fpu2.0-mxu2.0
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- description: Ingenic XBurst®2 CPU Cores
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enum:
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- ingenic,xburst2-fpu2.1-mxu2.1-smt
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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required:
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- device_type
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- compatible
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- reg
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- clocks
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examples:
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- |
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#include <dt-bindings/clock/jz4780-cgu.h>
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "ingenic,xburst-fpu1.0-mxu1.1";
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reg = <0>;
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clocks = <&cgu JZ4780_CLK_CPU>;
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clock-names = "cpu";
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "ingenic,xburst-fpu1.0-mxu1.1";
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reg = <1>;
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clocks = <&cgu JZ4780_CLK_CORE1>;
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clock-names = "cpu";
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};
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};
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...

‎Documentation/devicetree/bindings/mips/loongson/devices.yaml‎

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compatible:
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oneOf:
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- description: Generic Loongson3 Quad Core + RS780E
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- description: Classic Loongson64 Quad Core + LS7A
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items:
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- const: loongson,loongson3-4core-rs780e
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- const: loongson,loongson64c-4core-ls7a
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- description: Generic Loongson3 Octa Core + RS780E
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- description: Classic Loongson64 Quad Core + RS780E
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items:
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- const: loongson,loongson3-8core-rs780e
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- const: loongson,loongson64c-4core-rs780e
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- description: Classic Loongson64 Octa Core + RS780E
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items:
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- const: loongson,loongson64c-8core-rs780e
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- description: Generic Loongson64 Quad Core + LS7A
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items:
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- const: loongson,loongson64g-4core-ls7a
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- description: Virtual Loongson64 Quad Core + VirtIO
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items:
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- const: loongson,loongson64v-4core-virtio
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...

‎Documentation/devicetree/bindings/power/mti,mips-cpc.txt‎

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