Skip to content

Commit b73b737

Browse files
Aurabindo Pillaialexdeucher
Aurabindo Pillai
authored and
alexdeucher
committed
drm/amd/display: Add some missing register definitions
[Why&How] Add some missing register definitions and rearrange some others to maintain consistency with related definitions. Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1 parent f7d0157 commit b73b737

5 files changed

Lines changed: 58 additions & 30 deletions

File tree

‎drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h‎

Lines changed: 40 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -98,6 +98,29 @@
9898
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \
9999
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5)
100100

101+
#define HWSEQ_PIXEL_RATE_REG_LIST_302(blk) \
102+
SRII(PIXEL_RATE_CNTL, blk, 0), \
103+
SRII(PIXEL_RATE_CNTL, blk, 1),\
104+
SRII(PIXEL_RATE_CNTL, blk, 2),\
105+
SRII(PIXEL_RATE_CNTL, blk, 3), \
106+
SRII(PIXEL_RATE_CNTL, blk, 4)
107+
108+
#define HWSEQ_PHYPLL_REG_LIST_302(blk) \
109+
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
110+
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1),\
111+
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2),\
112+
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \
113+
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4)
114+
115+
#define HWSEQ_PIXEL_RATE_REG_LIST_303(blk) \
116+
SRII(PIXEL_RATE_CNTL, blk, 0), \
117+
SRII(PIXEL_RATE_CNTL, blk, 1)
118+
119+
#define HWSEQ_PHYPLL_REG_LIST_303(blk) \
120+
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
121+
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1)
122+
123+
101124
#define HWSEQ_PHYPLL_REG_LIST_201(blk) \
102125
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
103126
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1)
@@ -387,7 +410,11 @@
387410
SR(MPC_CRC_RESULT_C), \
388411
SR(MPC_CRC_RESULT_AR), \
389412
SR(AZALIA_AUDIO_DTO), \
390-
SR(AZALIA_CONTROLLER_CLOCK_GATING)
413+
SR(AZALIA_CONTROLLER_CLOCK_GATING), \
414+
SR(HPO_TOP_CLOCK_CONTROL), \
415+
SR(ODM_MEM_PWR_CTRL3), \
416+
SR(DMU_MEM_PWR_CNTL), \
417+
SR(MMHUBBUB_MEM_PWR_CNTL)
391418

392419
#define HWSEQ_DCN301_REG_LIST()\
393420
SR(REFCLK_CNTL), \
@@ -508,8 +535,11 @@
508535
SR(D5VGA_CONTROL), \
509536
SR(D6VGA_CONTROL), \
510537
SR(DC_IP_REQUEST_CNTL), \
538+
HWSEQ_PIXEL_RATE_REG_LIST_302(OTG), \
539+
HWSEQ_PHYPLL_REG_LIST_302(OTG), \
511540
SR(AZALIA_AUDIO_DTO), \
512-
SR(AZALIA_CONTROLLER_CLOCK_GATING)
541+
SR(AZALIA_CONTROLLER_CLOCK_GATING), \
542+
SR(HPO_TOP_CLOCK_CONTROL)
513543

514544
#define HWSEQ_DCN303_REG_LIST() \
515545
HWSEQ_DCN_REG_LIST(), \
@@ -540,28 +570,6 @@
540570
SR(AZALIA_CONTROLLER_CLOCK_GATING), \
541571
SR(HPO_TOP_CLOCK_CONTROL)
542572

543-
#define HWSEQ_PIXEL_RATE_REG_LIST_302(blk) \
544-
SRII(PIXEL_RATE_CNTL, blk, 0), \
545-
SRII(PIXEL_RATE_CNTL, blk, 1),\
546-
SRII(PIXEL_RATE_CNTL, blk, 2),\
547-
SRII(PIXEL_RATE_CNTL, blk, 3), \
548-
SRII(PIXEL_RATE_CNTL, blk, 4)
549-
550-
#define HWSEQ_PHYPLL_REG_LIST_302(blk) \
551-
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
552-
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1),\
553-
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2),\
554-
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \
555-
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4)
556-
557-
#define HWSEQ_PIXEL_RATE_REG_LIST_303(blk) \
558-
SRII(PIXEL_RATE_CNTL, blk, 0), \
559-
SRII(PIXEL_RATE_CNTL, blk, 1)
560-
561-
#define HWSEQ_PHYPLL_REG_LIST_303(blk) \
562-
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
563-
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1)
564-
565573
struct dce_hwseq_registers {
566574
uint32_t DCFE_CLOCK_CONTROL[6];
567575
uint32_t DCFEV_CLOCK_CONTROL;
@@ -663,14 +671,15 @@ struct dce_hwseq_registers {
663671
uint32_t MC_VM_XGMI_LFB_CNTL;
664672
uint32_t AZALIA_AUDIO_DTO;
665673
uint32_t AZALIA_CONTROLLER_CLOCK_GATING;
674+
/* MMHUB VM */
675+
uint32_t MC_VM_FB_LOCATION_BASE;
676+
uint32_t MC_VM_FB_LOCATION_TOP;
677+
uint32_t MC_VM_FB_OFFSET;
678+
uint32_t MMHUBBUB_MEM_PWR_CNTL;
666679
uint32_t HPO_TOP_CLOCK_CONTROL;
667680
uint32_t ODM_MEM_PWR_CTRL3;
668681
uint32_t DMU_MEM_PWR_CNTL;
669-
uint32_t MMHUBBUB_MEM_PWR_CNTL;
670682
uint32_t DCHUBBUB_ARB_HOSTVM_CNTL;
671-
uint32_t MC_VM_FB_LOCATION_BASE;
672-
uint32_t MC_VM_FB_LOCATION_TOP;
673-
uint32_t MC_VM_FB_OFFSET;
674683
uint32_t HPO_TOP_HW_CONTROL;
675684
};
676685
/* set field name */
@@ -915,6 +924,7 @@ struct dce_hwseq_registers {
915924
#define HWSEQ_DCN30_MASK_SH_LIST(mask_sh)\
916925
HWSEQ_DCN2_MASK_SH_LIST(mask_sh), \
917926
HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
927+
HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_GATE_DIS, mask_sh), \
918928
HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
919929
HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
920930
HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
@@ -1012,7 +1022,8 @@ struct dce_hwseq_registers {
10121022
HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN19_PGFSM_PWR_STATUS, mask_sh), \
10131023
HWS_SF(, DOMAIN20_PG_STATUS, DOMAIN20_PGFSM_PWR_STATUS, mask_sh), \
10141024
HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
1015-
HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh)
1025+
HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
1026+
HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_GATE_DIS, mask_sh)
10161027

10171028
#define HWSEQ_DCN303_MASK_SH_LIST(mask_sh) \
10181029
HWSEQ_DCN_MASK_SH_LIST(mask_sh), \

‎drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15805,6 +15805,11 @@
1580515805
#define mmDME6_DME_MEMORY_CONTROL 0x093d
1580615806
#define mmDME6_DME_MEMORY_CONTROL_BASE_IDX 3
1580715807

15808+
// addressBlock: dce_dc_hpo_hpo_top_dispdec
15809+
// base address: 0x0
15810+
#define mmHPO_TOP_CLOCK_CONTROL 0x0e43
15811+
#define mmHPO_TOP_CLOCK_CONTROL_BASE_IDX 3
15812+
1580815813
// base address: 0x1a698
1580915814
#define mmDC_PERFMON29_PERFCOUNTER_CNTL 0x0e66
1581015815
#define mmDC_PERFMON29_PERFCOUNTER_CNTL_BASE_IDX 3

‎drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -60666,7 +60666,12 @@
6066660666
#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L
6066760667
#define DME6_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L
6066860668

60669+
// addressBlock: dce_dc_hpo_hpo_top_dispdec
60670+
//HPO_TOP_CLOCK_CONTROL
60671+
#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_GATE_DIS__SHIFT 0x9
60672+
#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_GATE_DIS_MASK 0x00000200L
6066960673

60674+
// addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec
6067060675
//DC_PERFMON29_PERFCOUNTER_CNTL
6067160676
#define DC_PERFMON29_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
6067260677
#define DC_PERFMON29_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9

‎drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14205,6 +14205,10 @@
1420514205

1420614206

1420714207

14208+
// addressBlock: dce_dc_hpo_hpo_top_dispdec
14209+
// base address: 0x0
14210+
#define mmHPO_TOP_CLOCK_CONTROL 0x0e43
14211+
#define mmHPO_TOP_CLOCK_CONTROL_BASE_IDX 3
1420814212

1420914213
// base address: 0x1a698
1421014214
#define mmDC_PERFMON26_PERFCOUNTER_CNTL 0x0e66

‎drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_sh_mask.h‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -52401,7 +52401,10 @@
5240152401
#define DC_PERFMON25_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
5240252402
#define DC_PERFMON25_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
5240352403

52404-
52404+
// addressBlock: dce_dc_hpo_hpo_top_dispdec
52405+
//HPO_TOP_CLOCK_CONTROL
52406+
#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_GATE_DIS__SHIFT 0x9
52407+
#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_GATE_DIS_MASK 0x00000200L
5240552408

5240652409
// addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec
5240752410
//DC_PERFMON26_PERFCOUNTER_CNTL

0 commit comments

Comments
 (0)