Skip to content

Commit b73fd95

Browse files
Sam Protsenkokrzk
Sam Protsenko
authored and
krzk
committed
clk: samsung: exynos850: Implement CMU_AUD domain
CMU_AUD clock domain provides clocks for ABOX IP-core (audio subsystem). According to Exynos850 TRM, CMU_AUD generates Cortex-A32 clock, bus clock and audio clocks for BLK_AUD. This patch adds next clocks: - bus clocks in CMU_TOP needed for CMU_AUD - all internal CMU_AUD clocks - leaf clocks for Cortex-A32, Speedy FM, UAIF0..UAIF6 (Unified Audio Interface), CNT (counter), ABOX IP-core, ASB (Asynchronous Bridge), DAP (Debug Access Port), I2S Codec MCLK, D_TZPC (TrustZone Protection Controller), GPIO, PPMU (Platform Performance Monitoring Unit), SysMMU, SysReg and WDT ABOX clock was marked as CLK_IGNORE_UNUSED, as system hangs on boot otherwise. Once ABOX driver is implemented, maybe it can be handled there instead. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220809113323.29965-6-semen.protsenko@linaro.org
1 parent dbaa27c commit b73fd95

1 file changed

Lines changed: 302 additions & 0 deletions

File tree

‎drivers/clk/samsung/clk-exynos850.c‎

Lines changed: 302 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,7 @@
3030
#define PLL_CON0_PLL_SHARED1 0x0180
3131
#define PLL_CON3_PLL_SHARED1 0x018c
3232
#define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1000
33+
#define CLK_CON_MUX_MUX_CLKCMU_AUD 0x1004
3334
#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014
3435
#define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018
3536
#define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c
@@ -42,6 +43,7 @@
4243
#define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074
4344
#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078
4445
#define CLK_CON_DIV_CLKCMU_APM_BUS 0x180c
46+
#define CLK_CON_DIV_CLKCMU_AUD 0x1810
4547
#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1820
4648
#define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824
4749
#define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828
@@ -60,6 +62,7 @@
6062
#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c
6163
#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0
6264
#define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2008
65+
#define CLK_CON_GAT_GATE_CLKCMU_AUD 0x200c
6366
#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c
6467
#define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020
6568
#define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024
@@ -83,6 +86,7 @@ static const unsigned long top_clk_regs[] __initconst = {
8386
PLL_CON0_PLL_SHARED1,
8487
PLL_CON3_PLL_SHARED1,
8588
CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
89+
CLK_CON_MUX_MUX_CLKCMU_AUD,
8690
CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
8791
CLK_CON_MUX_MUX_CLKCMU_CORE_CCI,
8892
CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD,
@@ -95,6 +99,7 @@ static const unsigned long top_clk_regs[] __initconst = {
9599
CLK_CON_MUX_MUX_CLKCMU_PERI_IP,
96100
CLK_CON_MUX_MUX_CLKCMU_PERI_UART,
97101
CLK_CON_DIV_CLKCMU_APM_BUS,
102+
CLK_CON_DIV_CLKCMU_AUD,
98103
CLK_CON_DIV_CLKCMU_CORE_BUS,
99104
CLK_CON_DIV_CLKCMU_CORE_CCI,
100105
CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD,
@@ -113,6 +118,7 @@ static const unsigned long top_clk_regs[] __initconst = {
113118
CLK_CON_DIV_PLL_SHARED1_DIV3,
114119
CLK_CON_DIV_PLL_SHARED1_DIV4,
115120
CLK_CON_GAT_GATE_CLKCMU_APM_BUS,
121+
CLK_CON_GAT_GATE_CLKCMU_AUD,
116122
CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
117123
CLK_CON_GAT_GATE_CLKCMU_CORE_CCI,
118124
CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD,
@@ -148,6 +154,9 @@ PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
148154
PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
149155
/* List of parent clocks for Muxes in CMU_TOP: for CMU_APM */
150156
PNAME(mout_clkcmu_apm_bus_p) = { "dout_shared0_div4", "pll_shared1_div4" };
157+
/* List of parent clocks for Muxes in CMU_TOP: for CMU_AUD */
158+
PNAME(mout_aud_p) = { "fout_shared1_pll", "dout_shared0_div2",
159+
"dout_shared1_div2", "dout_shared0_div3" };
151160
/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
152161
PNAME(mout_core_bus_p) = { "dout_shared1_div2", "dout_shared0_div3",
153162
"dout_shared1_div3", "dout_shared0_div4" };
@@ -190,6 +199,10 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
190199
MUX(CLK_MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus",
191200
mout_clkcmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1),
192201

202+
/* AUD */
203+
MUX(CLK_MOUT_AUD, "mout_aud", mout_aud_p,
204+
CLK_CON_MUX_MUX_CLKCMU_AUD, 0, 2),
205+
193206
/* CORE */
194207
MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,
195208
CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
@@ -240,6 +253,10 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
240253
DIV(CLK_DOUT_CLKCMU_APM_BUS, "dout_clkcmu_apm_bus",
241254
"gout_clkcmu_apm_bus", CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
242255

256+
/* AUD */
257+
DIV(CLK_DOUT_AUD, "dout_aud", "gout_aud",
258+
CLK_CON_DIV_CLKCMU_AUD, 0, 4),
259+
243260
/* CORE */
244261
DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus",
245262
CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
@@ -286,6 +303,10 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
286303
GATE(CLK_GOUT_CLKCMU_APM_BUS, "gout_clkcmu_apm_bus",
287304
"mout_clkcmu_apm_bus", CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, 0, 0),
288305

306+
/* AUD */
307+
GATE(CLK_GOUT_AUD, "gout_aud", "mout_aud",
308+
CLK_CON_GAT_GATE_CLKCMU_AUD, 21, 0, 0),
309+
289310
/* DPU */
290311
GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu",
291312
CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0),
@@ -462,6 +483,284 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = {
462483
.clk_name = "dout_clkcmu_apm_bus",
463484
};
464485

486+
/* ---- CMU_AUD ------------------------------------------------------------- */
487+
488+
#define PLL_LOCKTIME_PLL_AUD 0x0000
489+
#define PLL_CON0_PLL_AUD 0x0100
490+
#define PLL_CON3_PLL_AUD 0x010c
491+
#define PLL_CON0_MUX_CLKCMU_AUD_CPU_USER 0x0600
492+
#define PLL_CON0_MUX_TICK_USB_USER 0x0610
493+
#define CLK_CON_MUX_MUX_CLK_AUD_CPU 0x1000
494+
#define CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH 0x1004
495+
#define CLK_CON_MUX_MUX_CLK_AUD_FM 0x1008
496+
#define CLK_CON_MUX_MUX_CLK_AUD_UAIF0 0x100c
497+
#define CLK_CON_MUX_MUX_CLK_AUD_UAIF1 0x1010
498+
#define CLK_CON_MUX_MUX_CLK_AUD_UAIF2 0x1014
499+
#define CLK_CON_MUX_MUX_CLK_AUD_UAIF3 0x1018
500+
#define CLK_CON_MUX_MUX_CLK_AUD_UAIF4 0x101c
501+
#define CLK_CON_MUX_MUX_CLK_AUD_UAIF5 0x1020
502+
#define CLK_CON_MUX_MUX_CLK_AUD_UAIF6 0x1024
503+
#define CLK_CON_DIV_DIV_CLK_AUD_MCLK 0x1800
504+
#define CLK_CON_DIV_DIV_CLK_AUD_AUDIF 0x1804
505+
#define CLK_CON_DIV_DIV_CLK_AUD_BUSD 0x1808
506+
#define CLK_CON_DIV_DIV_CLK_AUD_BUSP 0x180c
507+
#define CLK_CON_DIV_DIV_CLK_AUD_CNT 0x1810
508+
#define CLK_CON_DIV_DIV_CLK_AUD_CPU 0x1814
509+
#define CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK 0x1818
510+
#define CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG 0x181c
511+
#define CLK_CON_DIV_DIV_CLK_AUD_FM 0x1820
512+
#define CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY 0x1824
513+
#define CLK_CON_DIV_DIV_CLK_AUD_UAIF0 0x1828
514+
#define CLK_CON_DIV_DIV_CLK_AUD_UAIF1 0x182c
515+
#define CLK_CON_DIV_DIV_CLK_AUD_UAIF2 0x1830
516+
#define CLK_CON_DIV_DIV_CLK_AUD_UAIF3 0x1834
517+
#define CLK_CON_DIV_DIV_CLK_AUD_UAIF4 0x1838
518+
#define CLK_CON_DIV_DIV_CLK_AUD_UAIF5 0x183c
519+
#define CLK_CON_DIV_DIV_CLK_AUD_UAIF6 0x1840
520+
#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT 0x2000
521+
#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0 0x2004
522+
#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1 0x2008
523+
#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2 0x200c
524+
#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3 0x2010
525+
#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4 0x2014
526+
#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5 0x2018
527+
#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6 0x201c
528+
#define CLK_CON_GAT_GOUT_AUD_ABOX_ACLK 0x2048
529+
#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY 0x204c
530+
#define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB 0x2050
531+
#define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32 0x2054
532+
#define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP 0x2058
533+
#define CLK_CON_GAT_GOUT_AUD_CODEC_MCLK 0x206c
534+
#define CLK_CON_GAT_GOUT_AUD_TZPC_PCLK 0x2070
535+
#define CLK_CON_GAT_GOUT_AUD_GPIO_PCLK 0x2074
536+
#define CLK_CON_GAT_GOUT_AUD_PPMU_ACLK 0x2088
537+
#define CLK_CON_GAT_GOUT_AUD_PPMU_PCLK 0x208c
538+
#define CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1 0x20b4
539+
#define CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK 0x20b8
540+
#define CLK_CON_GAT_GOUT_AUD_WDT_PCLK 0x20bc
541+
542+
static const unsigned long aud_clk_regs[] __initconst = {
543+
PLL_LOCKTIME_PLL_AUD,
544+
PLL_CON0_PLL_AUD,
545+
PLL_CON3_PLL_AUD,
546+
PLL_CON0_MUX_CLKCMU_AUD_CPU_USER,
547+
PLL_CON0_MUX_TICK_USB_USER,
548+
CLK_CON_MUX_MUX_CLK_AUD_CPU,
549+
CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH,
550+
CLK_CON_MUX_MUX_CLK_AUD_FM,
551+
CLK_CON_MUX_MUX_CLK_AUD_UAIF0,
552+
CLK_CON_MUX_MUX_CLK_AUD_UAIF1,
553+
CLK_CON_MUX_MUX_CLK_AUD_UAIF2,
554+
CLK_CON_MUX_MUX_CLK_AUD_UAIF3,
555+
CLK_CON_MUX_MUX_CLK_AUD_UAIF4,
556+
CLK_CON_MUX_MUX_CLK_AUD_UAIF5,
557+
CLK_CON_MUX_MUX_CLK_AUD_UAIF6,
558+
CLK_CON_DIV_DIV_CLK_AUD_MCLK,
559+
CLK_CON_DIV_DIV_CLK_AUD_AUDIF,
560+
CLK_CON_DIV_DIV_CLK_AUD_BUSD,
561+
CLK_CON_DIV_DIV_CLK_AUD_BUSP,
562+
CLK_CON_DIV_DIV_CLK_AUD_CNT,
563+
CLK_CON_DIV_DIV_CLK_AUD_CPU,
564+
CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK,
565+
CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG,
566+
CLK_CON_DIV_DIV_CLK_AUD_FM,
567+
CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY,
568+
CLK_CON_DIV_DIV_CLK_AUD_UAIF0,
569+
CLK_CON_DIV_DIV_CLK_AUD_UAIF1,
570+
CLK_CON_DIV_DIV_CLK_AUD_UAIF2,
571+
CLK_CON_DIV_DIV_CLK_AUD_UAIF3,
572+
CLK_CON_DIV_DIV_CLK_AUD_UAIF4,
573+
CLK_CON_DIV_DIV_CLK_AUD_UAIF5,
574+
CLK_CON_DIV_DIV_CLK_AUD_UAIF6,
575+
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT,
576+
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0,
577+
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1,
578+
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2,
579+
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3,
580+
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4,
581+
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5,
582+
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6,
583+
CLK_CON_GAT_GOUT_AUD_ABOX_ACLK,
584+
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY,
585+
CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB,
586+
CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32,
587+
CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP,
588+
CLK_CON_GAT_GOUT_AUD_CODEC_MCLK,
589+
CLK_CON_GAT_GOUT_AUD_TZPC_PCLK,
590+
CLK_CON_GAT_GOUT_AUD_GPIO_PCLK,
591+
CLK_CON_GAT_GOUT_AUD_PPMU_ACLK,
592+
CLK_CON_GAT_GOUT_AUD_PPMU_PCLK,
593+
CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1,
594+
CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK,
595+
CLK_CON_GAT_GOUT_AUD_WDT_PCLK,
596+
};
597+
598+
/* List of parent clocks for Muxes in CMU_AUD */
599+
PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll" };
600+
PNAME(mout_aud_cpu_user_p) = { "oscclk", "dout_aud" };
601+
PNAME(mout_aud_cpu_p) = { "dout_aud_cpu", "mout_aud_cpu_user" };
602+
PNAME(mout_aud_cpu_hch_p) = { "mout_aud_cpu", "oscclk" };
603+
PNAME(mout_aud_uaif0_p) = { "dout_aud_uaif0", "ioclk_audiocdclk0" };
604+
PNAME(mout_aud_uaif1_p) = { "dout_aud_uaif1", "ioclk_audiocdclk1" };
605+
PNAME(mout_aud_uaif2_p) = { "dout_aud_uaif2", "ioclk_audiocdclk2" };
606+
PNAME(mout_aud_uaif3_p) = { "dout_aud_uaif3", "ioclk_audiocdclk3" };
607+
PNAME(mout_aud_uaif4_p) = { "dout_aud_uaif4", "ioclk_audiocdclk4" };
608+
PNAME(mout_aud_uaif5_p) = { "dout_aud_uaif5", "ioclk_audiocdclk5" };
609+
PNAME(mout_aud_uaif6_p) = { "dout_aud_uaif6", "ioclk_audiocdclk6" };
610+
PNAME(mout_aud_tick_usb_user_p) = { "oscclk", "tick_usb" };
611+
PNAME(mout_aud_fm_p) = { "oscclk", "dout_aud_fm_spdy" };
612+
613+
/*
614+
* Do not provide PLL table to PLL_AUD, as MANUAL_PLL_CTRL bit is not set
615+
* for that PLL by default, so set_rate operation would fail.
616+
*/
617+
static const struct samsung_pll_clock aud_pll_clks[] __initconst = {
618+
PLL(pll_0831x, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
619+
PLL_LOCKTIME_PLL_AUD, PLL_CON3_PLL_AUD, NULL),
620+
};
621+
622+
static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = {
623+
FRATE(IOCLK_AUDIOCDCLK0, "ioclk_audiocdclk0", NULL, 0, 25000000),
624+
FRATE(IOCLK_AUDIOCDCLK1, "ioclk_audiocdclk1", NULL, 0, 25000000),
625+
FRATE(IOCLK_AUDIOCDCLK2, "ioclk_audiocdclk2", NULL, 0, 25000000),
626+
FRATE(IOCLK_AUDIOCDCLK3, "ioclk_audiocdclk3", NULL, 0, 25000000),
627+
FRATE(IOCLK_AUDIOCDCLK4, "ioclk_audiocdclk4", NULL, 0, 25000000),
628+
FRATE(IOCLK_AUDIOCDCLK5, "ioclk_audiocdclk5", NULL, 0, 25000000),
629+
FRATE(IOCLK_AUDIOCDCLK6, "ioclk_audiocdclk6", NULL, 0, 25000000),
630+
FRATE(TICK_USB, "tick_usb", NULL, 0, 60000000),
631+
};
632+
633+
static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
634+
MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p,
635+
PLL_CON0_PLL_AUD, 4, 1),
636+
MUX(CLK_MOUT_AUD_CPU_USER, "mout_aud_cpu_user", mout_aud_cpu_user_p,
637+
PLL_CON0_MUX_CLKCMU_AUD_CPU_USER, 4, 1),
638+
MUX(CLK_MOUT_AUD_TICK_USB_USER, "mout_aud_tick_usb_user",
639+
mout_aud_tick_usb_user_p,
640+
PLL_CON0_MUX_TICK_USB_USER, 4, 1),
641+
MUX(CLK_MOUT_AUD_CPU, "mout_aud_cpu", mout_aud_cpu_p,
642+
CLK_CON_MUX_MUX_CLK_AUD_CPU, 0, 1),
643+
MUX(CLK_MOUT_AUD_CPU_HCH, "mout_aud_cpu_hch", mout_aud_cpu_hch_p,
644+
CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH, 0, 1),
645+
MUX(CLK_MOUT_AUD_UAIF0, "mout_aud_uaif0", mout_aud_uaif0_p,
646+
CLK_CON_MUX_MUX_CLK_AUD_UAIF0, 0, 1),
647+
MUX(CLK_MOUT_AUD_UAIF1, "mout_aud_uaif1", mout_aud_uaif1_p,
648+
CLK_CON_MUX_MUX_CLK_AUD_UAIF1, 0, 1),
649+
MUX(CLK_MOUT_AUD_UAIF2, "mout_aud_uaif2", mout_aud_uaif2_p,
650+
CLK_CON_MUX_MUX_CLK_AUD_UAIF2, 0, 1),
651+
MUX(CLK_MOUT_AUD_UAIF3, "mout_aud_uaif3", mout_aud_uaif3_p,
652+
CLK_CON_MUX_MUX_CLK_AUD_UAIF3, 0, 1),
653+
MUX(CLK_MOUT_AUD_UAIF4, "mout_aud_uaif4", mout_aud_uaif4_p,
654+
CLK_CON_MUX_MUX_CLK_AUD_UAIF4, 0, 1),
655+
MUX(CLK_MOUT_AUD_UAIF5, "mout_aud_uaif5", mout_aud_uaif5_p,
656+
CLK_CON_MUX_MUX_CLK_AUD_UAIF5, 0, 1),
657+
MUX(CLK_MOUT_AUD_UAIF6, "mout_aud_uaif6", mout_aud_uaif6_p,
658+
CLK_CON_MUX_MUX_CLK_AUD_UAIF6, 0, 1),
659+
MUX(CLK_MOUT_AUD_FM, "mout_aud_fm", mout_aud_fm_p,
660+
CLK_CON_MUX_MUX_CLK_AUD_FM, 0, 1),
661+
};
662+
663+
static const struct samsung_div_clock aud_div_clks[] __initconst = {
664+
DIV(CLK_DOUT_AUD_CPU, "dout_aud_cpu", "mout_aud_pll",
665+
CLK_CON_DIV_DIV_CLK_AUD_CPU, 0, 4),
666+
DIV(CLK_DOUT_AUD_BUSD, "dout_aud_busd", "mout_aud_pll",
667+
CLK_CON_DIV_DIV_CLK_AUD_BUSD, 0, 4),
668+
DIV(CLK_DOUT_AUD_BUSP, "dout_aud_busp", "mout_aud_pll",
669+
CLK_CON_DIV_DIV_CLK_AUD_BUSP, 0, 4),
670+
DIV(CLK_DOUT_AUD_AUDIF, "dout_aud_audif", "mout_aud_pll",
671+
CLK_CON_DIV_DIV_CLK_AUD_AUDIF, 0, 9),
672+
DIV(CLK_DOUT_AUD_CPU_ACLK, "dout_aud_cpu_aclk", "mout_aud_cpu_hch",
673+
CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, 0, 3),
674+
DIV(CLK_DOUT_AUD_CPU_PCLKDBG, "dout_aud_cpu_pclkdbg",
675+
"mout_aud_cpu_hch",
676+
CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, 0, 3),
677+
DIV(CLK_DOUT_AUD_MCLK, "dout_aud_mclk", "dout_aud_audif",
678+
CLK_CON_DIV_DIV_CLK_AUD_MCLK, 0, 2),
679+
DIV(CLK_DOUT_AUD_CNT, "dout_aud_cnt", "dout_aud_audif",
680+
CLK_CON_DIV_DIV_CLK_AUD_CNT, 0, 10),
681+
DIV(CLK_DOUT_AUD_UAIF0, "dout_aud_uaif0", "dout_aud_audif",
682+
CLK_CON_DIV_DIV_CLK_AUD_UAIF0, 0, 10),
683+
DIV(CLK_DOUT_AUD_UAIF1, "dout_aud_uaif1", "dout_aud_audif",
684+
CLK_CON_DIV_DIV_CLK_AUD_UAIF1, 0, 10),
685+
DIV(CLK_DOUT_AUD_UAIF2, "dout_aud_uaif2", "dout_aud_audif",
686+
CLK_CON_DIV_DIV_CLK_AUD_UAIF2, 0, 10),
687+
DIV(CLK_DOUT_AUD_UAIF3, "dout_aud_uaif3", "dout_aud_audif",
688+
CLK_CON_DIV_DIV_CLK_AUD_UAIF3, 0, 10),
689+
DIV(CLK_DOUT_AUD_UAIF4, "dout_aud_uaif4", "dout_aud_audif",
690+
CLK_CON_DIV_DIV_CLK_AUD_UAIF4, 0, 10),
691+
DIV(CLK_DOUT_AUD_UAIF5, "dout_aud_uaif5", "dout_aud_audif",
692+
CLK_CON_DIV_DIV_CLK_AUD_UAIF5, 0, 10),
693+
DIV(CLK_DOUT_AUD_UAIF6, "dout_aud_uaif6", "dout_aud_audif",
694+
CLK_CON_DIV_DIV_CLK_AUD_UAIF6, 0, 10),
695+
DIV(CLK_DOUT_AUD_FM_SPDY, "dout_aud_fm_spdy", "mout_aud_tick_usb_user",
696+
CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY, 0, 1),
697+
DIV(CLK_DOUT_AUD_FM, "dout_aud_fm", "mout_aud_fm",
698+
CLK_CON_DIV_DIV_CLK_AUD_FM, 0, 10),
699+
};
700+
701+
static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
702+
GATE(CLK_GOUT_AUD_CA32_CCLK, "gout_aud_ca32_cclk", "mout_aud_cpu_hch",
703+
CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 21, 0, 0),
704+
GATE(CLK_GOUT_AUD_ASB_CCLK, "gout_aud_asb_cclk", "dout_aud_cpu_aclk",
705+
CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, 21, 0, 0),
706+
GATE(CLK_GOUT_AUD_DAP_CCLK, "gout_aud_dap_cclk", "dout_aud_cpu_pclkdbg",
707+
CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP, 21, 0, 0),
708+
/* TODO: Should be enabled in ABOX driver (or made CLK_IS_CRITICAL) */
709+
GATE(CLK_GOUT_AUD_ABOX_ACLK, "gout_aud_abox_aclk", "dout_aud_busd",
710+
CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, 21, CLK_IGNORE_UNUSED, 0),
711+
GATE(CLK_GOUT_AUD_GPIO_PCLK, "gout_aud_gpio_pclk", "dout_aud_busd",
712+
CLK_CON_GAT_GOUT_AUD_GPIO_PCLK, 21, 0, 0),
713+
GATE(CLK_GOUT_AUD_PPMU_ACLK, "gout_aud_ppmu_aclk", "dout_aud_busd",
714+
CLK_CON_GAT_GOUT_AUD_PPMU_ACLK, 21, 0, 0),
715+
GATE(CLK_GOUT_AUD_PPMU_PCLK, "gout_aud_ppmu_pclk", "dout_aud_busd",
716+
CLK_CON_GAT_GOUT_AUD_PPMU_PCLK, 21, 0, 0),
717+
GATE(CLK_GOUT_AUD_SYSMMU_CLK, "gout_aud_sysmmu_clk", "dout_aud_busd",
718+
CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1, 21, 0, 0),
719+
GATE(CLK_GOUT_AUD_SYSREG_PCLK, "gout_aud_sysreg_pclk", "dout_aud_busd",
720+
CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK, 21, 0, 0),
721+
GATE(CLK_GOUT_AUD_WDT_PCLK, "gout_aud_wdt_pclk", "dout_aud_busd",
722+
CLK_CON_GAT_GOUT_AUD_WDT_PCLK, 21, 0, 0),
723+
GATE(CLK_GOUT_AUD_TZPC_PCLK, "gout_aud_tzpc_pclk", "dout_aud_busp",
724+
CLK_CON_GAT_GOUT_AUD_TZPC_PCLK, 21, 0, 0),
725+
GATE(CLK_GOUT_AUD_CODEC_MCLK, "gout_aud_codec_mclk", "dout_aud_mclk",
726+
CLK_CON_GAT_GOUT_AUD_CODEC_MCLK, 21, 0, 0),
727+
GATE(CLK_GOUT_AUD_CNT_BCLK, "gout_aud_cnt_bclk", "dout_aud_cnt",
728+
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT, 21, 0, 0),
729+
GATE(CLK_GOUT_AUD_UAIF0_BCLK, "gout_aud_uaif0_bclk", "mout_aud_uaif0",
730+
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0, 21, 0, 0),
731+
GATE(CLK_GOUT_AUD_UAIF1_BCLK, "gout_aud_uaif1_bclk", "mout_aud_uaif1",
732+
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1, 21, 0, 0),
733+
GATE(CLK_GOUT_AUD_UAIF2_BCLK, "gout_aud_uaif2_bclk", "mout_aud_uaif2",
734+
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2, 21, 0, 0),
735+
GATE(CLK_GOUT_AUD_UAIF3_BCLK, "gout_aud_uaif3_bclk", "mout_aud_uaif3",
736+
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3, 21, 0, 0),
737+
GATE(CLK_GOUT_AUD_UAIF4_BCLK, "gout_aud_uaif4_bclk", "mout_aud_uaif4",
738+
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, 21, 0, 0),
739+
GATE(CLK_GOUT_AUD_UAIF5_BCLK, "gout_aud_uaif5_bclk", "mout_aud_uaif5",
740+
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, 21, 0, 0),
741+
GATE(CLK_GOUT_AUD_UAIF6_BCLK, "gout_aud_uaif6_bclk", "mout_aud_uaif6",
742+
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, 21, 0, 0),
743+
GATE(CLK_GOUT_AUD_SPDY_BCLK, "gout_aud_spdy_bclk", "dout_aud_fm",
744+
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, 21, 0, 0),
745+
};
746+
747+
static const struct samsung_cmu_info aud_cmu_info __initconst = {
748+
.pll_clks = aud_pll_clks,
749+
.nr_pll_clks = ARRAY_SIZE(aud_pll_clks),
750+
.mux_clks = aud_mux_clks,
751+
.nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
752+
.div_clks = aud_div_clks,
753+
.nr_div_clks = ARRAY_SIZE(aud_div_clks),
754+
.gate_clks = aud_gate_clks,
755+
.nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
756+
.fixed_clks = aud_fixed_clks,
757+
.nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks),
758+
.nr_clk_ids = AUD_NR_CLK,
759+
.clk_regs = aud_clk_regs,
760+
.nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
761+
.clk_name = "dout_aud",
762+
};
763+
465764
/* ---- CMU_CMGP ------------------------------------------------------------ */
466765

467766
/* Register Offset definitions for CMU_CMGP (0x11c00000) */
@@ -1026,6 +1325,9 @@ static const struct of_device_id exynos850_cmu_of_match[] = {
10261325
{
10271326
.compatible = "samsung,exynos850-cmu-apm",
10281327
.data = &apm_cmu_info,
1328+
}, {
1329+
.compatible = "samsung,exynos850-cmu-aud",
1330+
.data = &aud_cmu_info,
10291331
}, {
10301332
.compatible = "samsung,exynos850-cmu-cmgp",
10311333
.data = &cmgp_cmu_info,

0 commit comments

Comments
 (0)